Class: SOCMaker::VerilogParser

Inherits:
HDLParser show all
Includes:
ERR, Singleton
Defined in:
lib/soc_maker/hdl_parser.rb

Instance Method Summary collapse

Methods included from ERR

#consistence_error, #consistence_error_if, #init_error, #init_error_if, #processing_error, #processing_error_if

Methods inherited from HDLParser

#get_all_hdl_files, #get_content, #get_extension, #parse_core

Constructor Details

#initialize ⇒ VerilogParser

Returns a new instance of VerilogParser.



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# File 'lib/soc_maker/hdl_parser.rb', line 184

def initialize

end

Instance Method Details

#extract_length(content) ⇒ Object 



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# File 'lib/soc_maker/hdl_parser.rb', line 247

def extract_length( content )

  numeric_regex   = /^\s*([0-9+\-\s]+):([0-9+\-\s]+)/
  parameter_regex = /^\s*(\D[\D\d]+)\s*-\s*1\s*:\s*0/


  content[ :port ].values.each do |port|
    if port[ :range ]
      if m = numeric_regex.match( port[ :range ] )
        tmp = " ( #{ m[1] } ) - ( #{ m[ 2 ] }  ) + 1 "
        begin
          port[ :length ] =  eval( tmp )
        rescue Exception
          port[:length] = 'UNKNOWN'
        end

      elsif m = parameter_regex.match( port[ :range ] )
          port[:length] = m[1]
      end
    else
      port[ :length ] = 1
    end
  end
  return content
end

#parse_package(data) ⇒ Object 



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# File 'lib/soc_maker/hdl_parser.rb', line 273

def parse_package( data )
  result = {}
 #data.split("\n").each do |line|
 #end
  return result
end

#parse_toplevel(data) ⇒ Object 



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# File 'lib/soc_maker/hdl_parser.rb', line 188

def parse_toplevel( data )
  # remove all newlines
  data = data.gsub( "\n", " " )

  # empty result hash
  result = {}

  module_regex    = /\s*module\s+(\w+)*\s*\(.*?\);/
  port_regex      = /(input|output)\s*(\[([\d\w\-\:\s]*)\s*\])?\s*(\w*);/
  parameter_regex = /parameter\s*(\w*)\s*=\s(.*?);/


  # extract module name
  if m = module_regex.match( data )
    result[ :name ] = m[1]
  else
    result[ :name ] = "unknown"
  end

  #
  # extract parameteters
  #
  parameters = data.scan( parameter_regex )
  result[ :generic ] = {}
  parameters.each do |port|

    result[ :generic ][ port[0] ] = { name: port[0], default: port[1], type: "integer" }

  end

  #
  # extract ports
  #
  ports = data.scan( port_regex )
  result[ :port ] = {}
  ports.each do |port|
    result[ :port ][ port[3] ] = { name: port[3] }


    if port[0] 
      if port[0] == "input"
        result[ :port ][ port[3] ][ :dir ] = "in"
      elsif port[0] == "output"
        result[ :port ][ port[3] ][ :dir ] = "out"
      else
        result[ :port ][ port[3] ][ :dir ] = "in"
      end
    end


    if port[ 2 ]
      result[ :port ][ port[ 3 ] ][ :range ] = port[ 2 ]
    end

  end

  return result
end