Class: SOCMaker::HDLParser

Inherits:
Object
  • Object
show all
Includes:
ERR, Singleton
Defined in:
lib/soc_maker/hdl_parser.rb

Direct Known Subclasses

VHDLParser, VerilogParser

Instance Method Summary collapse

Methods included from ERR

#consistence_error, #consistence_error_if, #init_error, #init_error_if, #processing_error, #processing_error_if

Constructor Details

#initialize ⇒ HDLParser

Returns a new instance of HDLParser.



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# File 'lib/soc_maker/hdl_parser.rb', line 57

def initialize

end

Instance Method Details

#get_all_hdl_files(files) ⇒ Object 



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# File 'lib/soc_maker/hdl_parser.rb', line 71

def get_all_hdl_files( files )
  hdl_files = []
  files.each { |f|   hdl_files += Dir[f] }
  return hdl_files
end

#get_content(file) ⇒ Object 



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# File 'lib/soc_maker/hdl_parser.rb', line 62

def get_content( file )
  return File.open( file, "r"){ |f| f.read }
end

#get_extension(file) ⇒ Object 



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# File 'lib/soc_maker/hdl_parser.rb', line 67

def get_extension( file )
  return File.extname( file )
end

#parse_core(top_file, files, package_file = nil) ⇒ Object 



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# File 'lib/soc_maker/hdl_parser.rb', line 80

def parse_core( top_file, files, package_file = nil )

  files = [ files ] if not files.kind_of?( Array )

  #
  # read and parse toplevel file
  #
  content = get_content( top_file )
  if get_extension( top_file ) == ".v" 
    toplevel = VerilogParser.instance.parse_toplevel( content )
    toplevel = VerilogParser.instance.extract_length( toplevel )
  elsif get_extension( top_file ) == ".vhd"
    toplevel = VHDLParser.instance.parse_toplevel( content )
    toplevel = VHDLParser.instance.extract_length( toplevel )
  end

  #
  # read and parse package file
  #
  #   -> not yet supported
  # 
  if package_file != nil
    content = get_content( package_file )
    if get_extension( package_file ) == ".v"
      package = VerilogParser.instance.parse_package( content )
    elsif get_extension( top_file ) == ".vhd"
      package = VerilogParser.instance.parse_package( content )
    end
  else
    package = {}
  end


  #
  # get all HDL files
  #
  hdl_files = get_all_hdl_files( files )



  #
  # Prepare options and ports hashes
  #
  options = { 'inst_parameters' => {},
              'hdlfiles'        => {},
              'interfaces'      => {} }

  if toplevel.has_key?( :generic )
    toplevel[ :generic ].values.each do | v |
      options[ 'inst_parameters' ][ v[:name] ] = Parameter.new( v[ :type ], default: v[ :default ] )
    end
  end

  ports = {}
  if toplevel.has_key?( :port )
    toplevel[ :port ].values.each do | v |
      ports[ v[ :name ] ] = IfcPort.new( v[:name], v[:length]  )
    end
  end

  ifc_name = toplevel[:name].to_s + '_ifc'
  ifc_id   = ifc_name + ",v1"
  options[ 'interfaces'][ ifc_name ] = IfcDef.new( ifc_name, ifc_id, 0, ports )

  hdl_files.each do | f |
    f_opts = {}
    name = Pathname.new( f ).basename( ".*" ).to_s
    if name.include? "sim"
      f_opts[ 'use_syn'     => false ]
      f_opts[ 'use_mod_sim' => true  ]
    else
      f_opts[ 'use_syn'     => true  ]
      f_opts[ 'use_mod_sim' => false ]
    end
    options[ 'hdlfiles' ][ name ] = HDLFile.new( f, f_opts )
  end

  #
  # create new core
  #
  d = CoreDef.new( toplevel[ :name ], 
                   toplevel[ :name ]+",v1",
                   toplevel[ :name ], options)



  # dump the result
  return SOCMaker::to_yaml_s( d )

end