Class: SOCMaker::HDLFile

Inherits:
Object
  • Object
show all
Includes:
ERR
Defined in:
lib/soc_maker/hdl_file.rb

Overview

A small classes, used to group information and to verify, auto-correct and auto-complete this information: The class represents an high-level-description (HDL) file. The two supported file-types are *.vhdl and *.v, whose information is stored in #type (‘verilog’ or ‘vhdl’). A #path is mandatory and defines, where the file is located. In addition, is is used for auto-detecting the file-type (if not given). There are three flags:

  • #use_syn (use in synthesis)

  • #use_sys_sim (use in system simulation)

  • #use_mod_sim (use in module simulation)

These flags are not used at the moment and reserved for future implementation.

Instance Attribute Summary collapse

Instance Method Summary collapse

Methods included from ERR

#consistence_error, #consistence_error_if, #init_error, #init_error_if, #processing_error, #processing_error_if

Constructor Details

#initialize(path, optional = {}) ⇒ HDLFile

The constructor gets the path as mandatory argument. Everything else can be passed with optional arguments



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# File 'lib/soc_maker/hdl_file.rb', line 81

def initialize( path, optional = {} )
  init_with( { 'path' => path }.merge( optional ) )
end

Instance Attribute Details

#path ⇒ Object

file path of the HDL file



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# File 'lib/soc_maker/hdl_file.rb', line 65

def path
  @path
end

#type ⇒ Object

type of this hdl file: ‘vhdl’ or ‘verilog’



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# File 'lib/soc_maker/hdl_file.rb', line 77

def type
  @type
end

#use_mod_sim ⇒ Object

modul simulation flag (reserved and not used)



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# File 'lib/soc_maker/hdl_file.rb', line 74

def use_mod_sim
  @use_mod_sim
end

#use_syn ⇒ Object

synthesis flag



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# File 'lib/soc_maker/hdl_file.rb', line 68

def use_syn
  @use_syn
end

#use_sys_sim ⇒ Object

system simulation flag (reserved and not used)



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# File 'lib/soc_maker/hdl_file.rb', line 71

def use_sys_sim
  @use_sys_sim
end

Instance Method Details

#==(o) ⇒ Object

Equality operator



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# File 'lib/soc_maker/hdl_file.rb', line 153

def ==(o)
  o.class           == self.class         &&
  o.path            == self.path          &&
  o.use_syn         == self.use_syn       &&
  o.use_sys_sim     == self.use_sys_sim   &&
  o.use_mod_sim     == self.use_mod_sim   &&
  o.type            == self.type         
end

#encode_with(coder) ⇒ Object

Encoder method (to yaml)

coder

An instance of the Psych::Coder to encode this class to a YAML file



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# File 'lib/soc_maker/hdl_file.rb', line 90

def encode_with( coder )
  init_error_if !coder.is_a?( Psych::Coder ), 
              'coder is not given as Psych::Coder'
  %w[ path use_syn use_sys_sim use_mod_sim type ].
    each { |v| coder[ v ] = instance_variable_get "@#{v}" }
end

#init_with(coder) ⇒ Object

Initialization method (from yaml)

coder

An instance of the Psych::Coder to init this class from a YAML file



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# File 'lib/soc_maker/hdl_file.rb', line 103

def init_with( coder )

  init_error_if !( coder.is_a?( Hash ) || coder.is_a?( Psych::Coder ) ), 
              'coder is not given as Hash neither as Psych::Coder'

  # check path
  init_error 'no filepath specified' if coder[ 'path' ] == nil
  @path = coder[ 'path' ]
  init_error 'path must be of type string' if !@path.is_a?( String )

  # auto-complete to 'true'
  @use_syn      = coder[ 'use_syn'     ] || true
  @use_sys_sim  = coder[ 'use_sys_sim' ] || true
  @use_mod_sim  = coder[ 'use_mod_sim' ] || true

  # ensure, that the thee use... fields are boolean
  init_error 'use_syn field must be true of false' if !!@use_syn != @use_syn
  init_error 'use_sys_sim field must be true of false' if !!@use_sys_sim != @use_sys_sim
  init_error 'use_mod_sim field must be true of false' if !!@use_mod_sim != @use_mod_sim 

  # if the file-type is not given, we try to auto-detect it
  #   *.vhd  ->  vhdl
  #   *.v    ->  verilog
  #   (see conf[ :vhdl_file_regex ] and 
  #        conf[ :verilog_file_regex ] )
  if  coder[ 'type' ] == nil 
    if @path =~ SOCMaker::conf[ :vhdl_file_regex ]
      SOCMaker::logger.warn "Auto-detected vhdl file type for #{ @path }"
      @type = 'vhdl'
    elsif @path =~ SOCMaker::conf[ :verilog_file_regex ]
      SOCMaker::logger.warn "Auto-detected verilog file type for #{ @path }"
      @type = 'verilog'
    else
      init_error "Cant auto-detect file type for #{path}" 
    end
  else
    # if the file-type is given, ensure, that it is either 'vhdl' or 'verilog'
    init_error  "The type must be 'vhdl' or 'verilog'",
      instance: @path,
      field:    'type' if !SOCMaker::conf[ :hdl_type_regex ].match( coder[ 'type' ] )
    @type = coder[ 'type' ]
  end

end