Class: VerilogParser::Module::Port

Inherits:
Object
  • Object
show all
Defined in:
lib/ruby-vpi/verilog_parser.rb

Instance Attribute Summary collapse

Instance Method Summary collapse

Constructor Details

#initialize(aDecl, aModule) ⇒ Port

Returns a new instance of Port.



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# File 'lib/ruby-vpi/verilog_parser.rb', line 47

def initialize aDecl, aModule
  @decl = aDecl
  @name = aDecl.scan(/\S+/).last

  parser = /\b(input|output|inout)\b[^;]*\b#{@name}\b/m
  aDecl =~ parser || aModule.body =~ parser
  @type = $1
end

Instance Attribute Details

#decl ⇒ Object (readonly)

Returns the value of attribute decl.



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# File 'lib/ruby-vpi/verilog_parser.rb', line 45

def decl
  @decl
end

#name ⇒ Object (readonly)

Returns the value of attribute name.



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# File 'lib/ruby-vpi/verilog_parser.rb', line 45

def name
  @name
end

Instance Method Details

#input? ⇒ Boolean

Returns:

  • (Boolean) 


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# File 'lib/ruby-vpi/verilog_parser.rb', line 56

def input?
  @type != 'output'
end

#output? ⇒ Boolean

Returns:

  • (Boolean) 


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# File 'lib/ruby-vpi/verilog_parser.rb', line 60

def output?
  @type != 'input'
end