Class: OrigenSimDev::DUT

Inherits:
Object
  • Object
show all
Includes:
Origen::TopLevel, OrigenJTAG
Defined in:
lib/origen_sim_dev/dut.rb

Constant Summary collapse

JTAG_CONFIG = 
{
  tclk_format: :rl
}

Instance Method Summary collapse

Methods included from Origen::TopLevel

#rtl_pins

Constructor Details

#initialize(options = {}) ⇒ DUT

Returns a new instance of DUT.



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# File 'lib/origen_sim_dev/dut.rb', line 10

def initialize(options = {})
  add_pin :tck, reset: :drive_lo
  add_pin :tdi, reset: :drive_lo
  add_pin :tdo
  add_pin :tms, reset: :drive_lo
  add_pin :rstn, reset: :drive_lo
  add_pin :trstn, reset: :drive_lo
  add_pin_alias :tclk, :tck
  add_pin :dout, size: 32
  add_pin :din_port, size: 32, rtl_name: 'din', reset: :drive_lo
  add_pin :p1, tie_off: 0
  add_pin :p2, tie_off: 1
  add_pin :p3, size: 4, tie_off: 0
  add_pin :p4, size: 4, tie_off: 1
  add_pin :v1, rtl_name: 'nc'
  add_pin :v2, rtl_name: :nc

  timeset :func do |t|
    # Generate a clock pulse on TCK
    t.wave :tck do |w|
      w.drive 0, at: 0
      w.drive :data, at: 'period / 2'
    end
  end

  add_reg :dr, 0x0, size: 66 do |reg|
    reg.bit 65, :rg_enable
    reg.bit 64, :rg_read
    reg.bits 63..32, :rg_addr
    reg.bits 31..0, :rg_data
  end

  add_reg :ctrl, 0x0 do |reg|
    reg.bit 0, :rg_enable
    reg.bit 1, :rg_reset
  end

  add_reg :cmd, 0x4

  add_reg :count, 0x8

  add_reg :data_out, 0xC

  add_reg :data_in, 0x10

  add_reg :p, 0x14 do |reg|
    reg.bits 0, :p1
    reg.bits 1, :p2
    reg.bits 5..2, :p3
    reg.bits 9..6, :p4
  end
end

Instance Method Details

#interactive_startup ⇒ Object 



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# File 'lib/origen_sim_dev/dut.rb', line 63

def interactive_startup
  if tester.sim?
    tester.start
    startup
  end
end

#read_register(reg, options = {}) ⇒ Object 



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# File 'lib/origen_sim_dev/dut.rb', line 90

def read_register(reg, options = {})
  jtag.write_ir(0x8, size: 4)
  dr.rg_enable.write(1)
  dr.rg_read.write(1)
  dr.rg_addr.write(reg.address)
  jtag.write_dr(dr)
  dr.rg_enable.write(0)
  dr.rg_data.copy_all(reg)
  jtag.read_dr(dr)
end

#startup(options = {}) ⇒ Object 



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# File 'lib/origen_sim_dev/dut.rb', line 70

def startup(options = {})
  tester.set_timeset('func', 100)

  dut.pin(:rstn).drive!(1)
  10.cycles
  dut.pin(:tck).drive!(1)
  10.cycles
  dut.pin(:trstn).drive!(1)
  10.cycles
end

#write_register(reg, options = {}) ⇒ Object 



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# File 'lib/origen_sim_dev/dut.rb', line 81

def write_register(reg, options = {})
  jtag.write_ir(0x8, size: 4)
  dr.rg_enable.write(1)
  dr.rg_read.write(0)
  dr.rg_addr.write(reg.address)
  dr.rg_data.write(reg.data)
  jtag.write_dr(dr)
end