Class: OrigenSimDev::DUT
- Inherits:
-
Object
- Object
- OrigenSimDev::DUT
- Includes:
- Origen::TopLevel, OrigenJTAG
- Defined in:
- lib/origen_sim_dev/dut.rb
Constant Summary collapse
- JTAG_CONFIG =
{ tclk_format: :rl }
Instance Method Summary collapse
-
#initialize(options = {}) ⇒ DUT
constructor
A new instance of DUT.
- #interactive_startup ⇒ Object
- #read_register(reg, options = {}) ⇒ Object
- #startup(options = {}) ⇒ Object
- #write_register(reg, options = {}) ⇒ Object
Methods included from Origen::TopLevel
Constructor Details
#initialize(options = {}) ⇒ DUT
Returns a new instance of DUT.
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 |
# File 'lib/origen_sim_dev/dut.rb', line 10 def initialize( = {}) add_pin :tck, reset: :drive_lo add_pin :tdi, reset: :drive_lo add_pin :tdo add_pin :tms, reset: :drive_lo add_pin :rstn, reset: :drive_lo add_pin :trstn, reset: :drive_lo add_pin_alias :tclk, :tck add_pin :dout, size: 32 add_pin :test_bus, size: 16 add_pin :din_port, size: 32, rtl_name: 'din', reset: :drive_lo add_pin :p1, force: 0 add_pin :p2, force: 1 add_pin :p3, size: 4, force: 0 add_pin :p4, size: 4, force: 0xA add_pin :v1, rtl_name: 'nc' add_pin :v2, rtl_name: :nc add_pin :not_present timeset :func do |t| # Generate a clock pulse on TCK t.wave :tck do |w| w.drive 0, at: 0 w.drive :data, at: 'period / 2' end end add_reg :dr, 0x0, size: 66 do |reg| reg.bit 65, :rg_enable reg.bit 64, :rg_read reg.bits 63..32, :rg_addr reg.bits 31..0, :rg_data end add_reg :ctrl, 0x0 do |reg| reg.bit 0, :rg_enable reg.bit 1, :rg_reset end add_reg :cmd, 0x4 add_reg :count, 0x8 add_reg :data_out, 0xC add_reg :data_in, 0x10 add_reg :p, 0x14 do |reg| reg.bits 0, :p1 reg.bits 1, :p2 reg.bits 5..2, :p3 reg.bits 9..6, :p4 end # Reg for testing parallel read/sync when this one is read the data will # be read out via dout rather than JTAG add_reg :parallel_read, 0x18 do |reg| reg.bits 30..28, :b1 reg.bits 26..24, :b2 reg.bits 18..16, :b3 reg.bits 14..12, :b4 reg.bits 6..4, :b5 reg.bits 2..0, :b6 end end |
Instance Method Details
#interactive_startup ⇒ Object
76 77 78 79 80 81 |
# File 'lib/origen_sim_dev/dut.rb', line 76 def interactive_startup if tester.sim? tester.start startup end end |
#read_register(reg, options = {}) ⇒ Object
104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 |
# File 'lib/origen_sim_dev/dut.rb', line 104 def read_register(reg, = {}) # Special read for this register to test sync'ing over a parallel if reg.id == :parallel_read pins = [] reg.shift_out_with_index do |bit, i| if bit.is_to_be_stored? pins << dut.pins(:dout)[i] end end tester.store_next_cycle(*pins.reverse) 1.cycle dut.pins(:dout).dont_care else jtag.write_ir(0x8, size: 4) dr.rg_enable.write(1) dr.rg_read.write(1) dr.rg_addr.write(reg.address) jtag.write_dr(dr) dr.rg_enable.write(0) dr.rg_data.copy_all(reg) jtag.read_dr(dr) end end |
#startup(options = {}) ⇒ Object
83 84 85 86 87 88 89 90 91 92 93 |
# File 'lib/origen_sim_dev/dut.rb', line 83 def startup( = {}) # tester.simulator.log_messages = true tester.set_timeset('func', 100) dut.pin(:rstn).drive!(1) 10.cycles dut.pin(:tck).drive!(1) 10.cycles dut.pin(:trstn).drive!(1) 10.cycles end |
#write_register(reg, options = {}) ⇒ Object
95 96 97 98 99 100 101 102 |
# File 'lib/origen_sim_dev/dut.rb', line 95 def write_register(reg, = {}) jtag.write_ir(0x8, size: 4) dr.rg_enable.write(1) dr.rg_read.write(0) dr.rg_addr.write(reg.address) dr.rg_data.write(reg.data) jtag.write_dr(dr) end |