Class: OrigenARMDebug::MemAP

Inherits:
AP
  • Object
show all
Defined in:
lib/origen_arm_debug/mem_ap.rb

Overview

Memory Access Port (MEM-AP)

Instance Attribute Summary collapse

Attributes inherited from AP

#apreg_access_wait

Instance Method Summary collapse

Constructor Details

#initialize(options = {}) ⇒ MemAP

Returns a new instance of MemAP.



12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
 
# File 'lib/origen_arm_debug/mem_ap.rb', line 12

def initialize(options = {})
  super

  @latency = options[:latency] || 0
  @apmem_access_wait = options[:apmem_access_wait] || 0

  reg :csw, 0x0 do |reg|
    reg.bit 31,     :dbg_sw_enable
    reg.bit 30..24, :prot
    reg.bit 23,     :spiden
    reg.bit 11..8,  :mode
    reg.bit 7,      :tr_in_prog
    reg.bit 6,      :device_en
    reg.bit 5..4,   :addr_inc
    reg.bit 2..0,   :size
  end
  reg(:csw).write(options[:csw_reset]) if options[:csw_reset]

  # Doesn't really reset to all 1's, but just to make sure the address
  # optimization logic does not kick in on the first transaction
  add_reg :tar, 0x04, reset: 0xFFFFFFFF
  add_reg :drw, 0x0C, reset: :undefined
  add_reg :bd0, 0x10, reset: :undefined
  add_reg :bd1, 0x14, reset: :undefined
  add_reg :bd2, 0x18, reset: :undefined
  add_reg :bd3, 0x1C, reset: :undefined

  reg :cfg, 0xF4, access: :ro do |reg|
    reg.bit 0, :big_endian
  end

  reg :base, 0xF8, access: :ro do |reg|
    reg.bit 31..12, :baseaddr
    reg.bit 1, :format, reset: 1
    reg.bit 0, :entry_present
  end

  add_reg :idr, 0xFC, access: :ro
end

Instance Attribute Details

#apmem_access_wait ⇒ Object

Wait states for data to be transferred from Memory Resource to DRW on

read request.  Should be added to apreg_access_wait for complete transaction
time of memory read (read data path: memory->drw->rdbuff)



10
11
12
 
# File 'lib/origen_arm_debug/mem_ap.rb', line 10

def apmem_access_wait
  @apmem_access_wait
end

#latency ⇒ Object

Latency to write a memory resource



5
6
7
 
# File 'lib/origen_arm_debug/mem_ap.rb', line 5

def latency
  @latency
end