Class: Logicuit::Circuits::Td4::Cpu

Inherits:
DSL
  • Object
show all
Defined in:
lib/logicuit/circuits/td4/cpu.rb

Overview

TD4 CPU

Instance Attribute Summary

Attributes inherited from DSL

#clock, #components, #initialized, #input_targets, #output_targets

Instance Method Summary collapse

Methods inherited from DSL

#[], assembling, #assembling, diagram, #evaluate, #initialize, #inputs, inputs, outputs, #outputs, run, truth_table

Constructor Details

This class inherits a constructor from Logicuit::DSL

Instance Method Details

#to_s ⇒ Object 



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# File 'lib/logicuit/circuits/td4/cpu.rb', line 47

def to_s
  p_a = "(#{@a || "0000"})"
  p_b = "(#{@b || "0000"})"

  register_a, register_b, pc, rom, dec = components
  @a = a = register_a[:qd, :qc, :qb, :qa].to_s
  @b = b = register_b[:qd, :qc, :qb, :qa].to_s
  p = pc[:qd, :qc, :qb, :qa]
  o = self[:led1, :led2, :led3, :led4]
  i = self[:in3, :in2, :in1, :in0]
  m = rom[:d3, :d2, :d1, :d0]
  c = "-(#{dec.c_flag})"
  loc = p.to_s.to_i(2)

  l1 = led1.current ? "*" : " "
  l2 = led2.current ? "*" : " "
  l3 = led3.current ? "*" : " "
  l4 = led4.current ? "*" : " "

  "\n      \#{l1 * 7}\#{\" \" * 7}\#{l2 * 7}\#{\" \" * 7}\#{l3 * 7}\#{\" \" * 7}\#{l4 * 7}\n     \#{l1 * 9}\#{\" \" * 5}\#{l2 * 9}\#{\" \" * 5}\#{l3 * 9}\#{\" \" * 5}\#{l4 * 9}\n    \#{l1 * 11}\#{\" \" * 3}\#{l2 * 11}\#{\" \" * 3}\#{l3 * 11}\#{\" \" * 3}\#{l4 * 11}\n     \#{l1 * 9}\#{\" \" * 5}\#{l2 * 9}\#{\" \" * 5}\#{l3 * 9}\#{\" \" * 5}\#{l4 * 9}\n      \#{l1 * 7}\#{\" \" * 7}\#{l2 * 7}\#{\" \" * 7}\#{l3 * 7}\#{\" \" * 7}\#{l4 * 7}\n\n    +-----------------------------------------------+     \#{loc ==  0 ? \">\" : \" \"} OUT 0111\n    |                                               |     \#{loc ==  1 ? \">\" : \" \"} ADD A,0001\n    +--->|rg_a|\#{p_a}----->|   |                    |     \#{loc ==  2 ? \">\" : \" \"} JNC 0001\n    |    |\#{a}|            |   |                    |     \#{loc ==  3 ? \">\" : \" \"} ADD A,0001\n    |                      |   |                    |     \#{loc ==  4 ? \">\" : \" \"} JNC 0011\n    +--->|rg_b|\#{p_b}----->|   |----------->|   |---+     \#{loc ==  5 ? \">\" : \" \"} OUT 0110\n    |    |\#{b}|            |   |            |   |         \#{loc ==  6 ? \">\" : \" \"} ADD A,0001\n    |                      |SEL|            |ALU|         \#{loc ==  7 ? \">\" : \" \"} JNC 0110\n    +--->| out|  |  in|--->|   |            |   |         \#{loc ==  8 ? \">\" : \" \"} ADD A,0001\n    |    |\#{o}|  |\#{i}|    |   |  |  im|--->|   |-\#{c}    \#{loc ==  9 ? \">\" : \" \"} JNC 1000\n    |                      |   |  |\#{m}|                  \#{loc == 10 ? \">\" : \" \"} OUT 0000\n    +--->|  pc|  (0000)--->|   |                          \#{loc == 11 ? \">\" : \" \"} OUT 0100\n         |\#{p}|                                           \#{loc == 12 ? \">\" : \" \"} ADD A,0001\n                                                          \#{loc == 13 ? \">\" : \" \"} JNC 1010\n                                                          \#{loc == 14 ? \">\" : \" \"} OUT 1000\n                                                          \#{loc == 15 ? \">\" : \" \"} JMP 1111\n  OUTPUT\nend\n"