Module: Indis::ARM::InstructionHelper
Constant Summary
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- COND =
[".EQ", ".NE", ".CS", ".CC", ".MI", ".PL", ".VS", ".VC", ".HI", ".LS", ".GE", ".LT", ".GT", ".LE", ""]
- COND_SYM =
[:eq, :ne, :cs, :cc, :mi, :pl, :vs, :vc, :hi, :ls, :ge, :lt, :gt, :le, :al]
- NAMED_REG =
{ r13: :sp, r14: :lr, r15: :pc }
- REG =
[:r0, :r1, :r2, :r3, :r4, :r5, :r6, :r7, :r8, :r9, :r10, :r11, :r12, :r13, :r14, :r15]
- SHIFT_TYPES =
{
SRType_LSL: :lsl,
SRType_LSR: :lsr,
SRType_ASR: :asr,
SRType_ROR: :ror,
SRType_RRX: :rrx,
}
Class Method Summary
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ARMExpandImm, ARMExpandImm_C, DecodeImmShift, LSL, LSL_C, LSR, LSR_C, ROR_C, Shift_C, SignExtend, ZeroExtend
Class Method Details
.cond(i) ⇒ Object
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# File 'lib/indis-arm/instruction_helper.rb', line 148
def cond(i)
COND_SYM[i]
end
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.cond_to_s(cond) ⇒ Object
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# File 'lib/indis-arm/instruction_helper.rb', line 130
def cond_to_s(cond)
('.' + cond.to_s.upcase).sub('.AL', '')
end
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.flag(f, fn) ⇒ Object
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# File 'lib/indis-arm/instruction_helper.rb', line 139
def flag(f, fn)
f ? fn : ''
end
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.reg(i) ⇒ Object
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# File 'lib/indis-arm/instruction_helper.rb', line 143
def reg(i)
r = REG[i]
NAMED_REG[r] || r
end
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.regs_from_bits(bits_list) ⇒ Object
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# File 'lib/indis-arm/instruction_helper.rb', line 115
def regs_from_bits(bits_list)
bl = bits_list.to_s(2)
bl = ('0'*(16-bl.length)) + bl
regs = []
bl.reverse! bl.length.times do |i|
regs << "r#{i}".to_sym if bl[i] == '1'
end
regs
end
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.regs_to_s(regs) ⇒ Object
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# File 'lib/indis-arm/instruction_helper.rb', line 134
def regs_to_s(regs)
regs = regs.map { |r| NAMED_REG[r] || r }
regs.join(', ')
end
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.shift_type_to_s(shift) ⇒ Object
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# File 'lib/indis-arm/instruction_helper.rb', line 126
def shift_type_to_s(shift)
SHIFT_TYPES[shift]
end
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