Class: CrossOrigenDev::DUT::D_IP_ANA_TEST_ANNEX_SYN

Inherits:
Object
  • Object
show all
Includes:
CrossOrigen, Origen::Model
Defined in:
lib/cross_origen_dev/dut.rb

Overview

rubocop:disable ClassAndModuleCamelCase

Instance Method Summary collapse

Methods included from CrossOrigen

#cr_cmsis_svd, #cr_design_sync, #cr_headers, #cr_import, #cr_ip_xact, #cr_ralf, #cr_try, include_timestamp=, include_timestamp?, #instance_respond_to?, refresh?, #to_header, #to_ip_xact, #to_ralf

Constructor Details

#initialize ⇒ D_IP_ANA_TEST_ANNEX_SYN

Returns a new instance of D_IP_ANA_TEST_ANNEX_SYN.



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# File 'lib/cross_origen_dev/dut.rb', line 42

def initialize
  # A manually defined register for testing the conversion of any specific attributes

  # ** MGATE Clock Divider Register **
  # The MCLKDIV register is used to divide down the frequency of the HBOSCCLK input. If the MCLKDIV
  # register is set to value "N", then the output (beat) frequency of the clock divider is OSCCLK / (N+1). The
  # resulting beats are, in turn, counted by the PTIMER module to control the duration of Flash high-voltage
  # operations.
  # This is a test of potentially problematic characters ' " \' \" < >
  reg :mclkdiv, 0x0, size: 16, bit_order: 'decrement' do
    # **Oscillator (Hi)** - Firmware FMU clk source selection. (Note that in addition to this firmware-controlled bit, the
    # FMU clock source is also dependent on test and power control discretes).
    #
    # 0 | FMU clock is the externally supplied bus clock ipg_clk
    # 1 | FMU clock is the internal oscillator from the TFS hardblock
    bit 15, :osch, reset: 1, access: :rw
  end
end