Class: ClassHDL::ImplicitPortOutput

Inherits:
ImplicitPortBase show all
Defined in:
lib/tdl/class_hdl/hdl_module_def.rb

Instance Attribute Summary

Attributes inherited from ImplicitPortBase

#_struct_q, #chain, #sdlm, #speciel_type, #sub_type

Instance Method Summary collapse

Methods inherited from ImplicitPortBase

#-, #[], #add_struct_method, #clock, #initialize, #logic, #method_missing, #reset, #wire

Constructor Details

This class inherits a constructor from ClassHDL::ImplicitPortBase

Dynamic Method Handling

This class handles dynamic methods through the method_missing method in the class ClassHDL::ImplicitPortBase

Instance Method Details

#sdlm_port(method, args) ⇒ Object 



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# File 'lib/tdl/class_hdl/hdl_module_def.rb', line 332

def sdlm_port(method,args)
    if @clock_freqM
        @sdlm.Clock(method,freqM: @clock_freqM,port: :output,pin:args[:pin]||[],iostd:args[:iostd]||[],dsize:args[:dsize]||1,pin_prop:args[:pin_prop])
    elsif @reset_active
        @sdlm.Reset(method,port: :output,active: @reset_active,pin:args[:pin]||[],iostd:args[:iostd]||[],dsize:args[:dsize]||1,pin_prop:args[:pin_prop])
    else 
        # if !args[:pin] && !args[:pin_prop] && @sdlm.is_a?(TopModule)
        #     @sdlm.Def.logic(name: method,dsize: args[:dsize] || 1 ,port:false, dimension:args[:dimension]||[])
        # else
        # puts @sdlm
        # puts @sdlm.parse_pin_prop(args[:pin_prop])
        # raise("-----")
        
        if args && args[:pin_prop] && args[:pin_prop]["pins"]
            pin = args[:pin_prop]["pins"]
            if  (["LOGIC","WIRE","TRI0","TRI1"].include? pin.to_s.upcase)
                a = @sdlm.Def.logic(name:method,dsize:args[:dsize]||1,dimension:args[:dimension] || [] )
                return a
            end
        end
        
        rel = @sdlm.Output(method,dsize:args[:dsize] || 1,dimension:args[:dimension]||[],pin:args[:pin]||[],iostd:args[:iostd]||[],pin_prop:args[:pin_prop])
        rel.type = @speciel_type
        add_struct_method(rel)
        rel
        
    end
end