Class: VerilogTools::Parser
- Inherits:
-
Object
- Object
- VerilogTools::Parser
- Defined in:
- lib/HDLRuby/verilog_parser.rb
Overview
The class of the parser.
Constant Summary collapse
- FS_TIME =
The table of time conversion.
{ "s" => 1_000_000_000_000_000, "ms" => 1_000_000_000_000, "us" => 1_000_000_000, "ns" => 1_000_000, "ps" => 1_000, "fs" => 1 }
- COMMA_TOK =
Definition of the tokens
","- SEMICOLON_TOK =
";"- COLON_TOK =
":"- OPEN_PAR_TOK =
"("- CLOSE_PAR_TOK =
")"- OPEN_BRA_TOK =
"["- CLOSE_BRA_TOK =
"]"- OPEN_CUR_TOK =
"{"- CLOSE_CUR_TOK =
"}"- SHARP_TOK =
"#"- AT_TOK =
"@"- DOT_TOK =
"."- EE_TOK =
"E"- Ee_TOK =
"e"- SLASH_TOK =
"/"- SLASH_SLASH_TOK =
"//"- SLASH_ASTERISK_TOK =
"/*"- ASTERISK_SLASH_TOK =
"*/"- EOL_TOK =
"\n"- MODULE_TOK =
"module"- MACROMODULE_TOK =
"macromodule"- ENDMODULE_TOK =
"endmodule"- PRIMITIVE_TOK =
"primitive"- ENDPRIMITIVE_TOK =
"endprimitive"- TASK_TOK =
"task"- ENDTASK_TOK =
"endtask"- FUNCTION_TOK =
"function"- ENDFUNCTION_TOK =
"endfunction"- TABLE_TOK =
"table"- ENDTABLE_TOK =
"endtable"- SPECIFY_TOK =
"specify"- ENDSPECIFY_TOK =
"endspecify"- INPUT_TOK =
"input"- OUTPUT_TOK =
"output"- INOUT_TOK =
"inout"- INITIAL_TOK =
"initial"- SPECPARAM_TOK =
"specparam"- IF_TOK =
"if"- ELSE_TOK =
"else"- CASE_TOK =
"case"- CASEZ_TOK =
"casez"- CASEX_TOK =
"casex"- ENDCASE_TOK =
"endcase"- FOREVER_TOK =
"forever"- REPEAT_TOK =
"repeat"- WHILE_TOK =
"while"- FOR_TOK =
"for"- WAIT_TOK =
"wait"- RIGHT_ARROW_TOK =
"->"- DISABLE_TOK =
"disable"- ASSIGN_TOK =
"assign"- DEASSIGN_TOK =
"deassign"- FORCE_TOK =
"force"- RELEASE_TOK =
"release"- ALWAYS_TOK =
"always"- DEFAULT_TOK =
"default"- BEGIN_TOK =
"begin"- END_TOK =
"end"- FORK_TOK =
"fork"- JOIN_TOK =
"join"- SIGNED_TOK =
"signed"- REG_TOK =
"reg"- TIME_TOK =
"time"- INTEGER_TOK =
"integer"- REAL_TOK =
"real"- EVENT_TOK =
"event"- DEFPARAM_TOK =
"defparam"- PARAMETER_TOK =
"parameter"- LOCALPARAM_TOK =
"localparam"- SCALARED_TOK =
"scalared"- VECTORED_TOK =
"vectored"- SETUP_TOK =
"$setup"- HOLD_TOK =
"$hold"- PERIOD_TOK =
"$period"- WIDTH_TOK =
"$width"- SKEW_TOK =
"$skew"- RECOVERY_TOK =
"$recovery"- SETUPHOLD_TOK =
"$setuphold"- HYPHEN_TOK =
"-"- ZERO_TOK =
"0"- ONE_TOK =
"1"- Xx_TOK =
"x"- XX_TOK =
"X"- Bb_TOK =
"b"- BB_TOK =
"B"- QUESTION_TOK =
"?"- Rr_TOK =
"r"- RR_TOK =
"R"- Ff_TOK =
"f"- FF_TOK =
"F"- Pp_TOK =
"p"- PP_TOK =
"P"- Nn_TOK =
"n"- NN_TOK =
"N"- ASTERISK_TOK =
"*"- Q_b_TOK =
"'b"- Q_B_TOK =
"'B"- Q_o_TOK =
"'o"- Q_O_TOK =
"'O"- Q_d_TOK =
"'d"- Q_D_TOK =
"'D"- Q_h_TOK =
"'h"- Q_H_TOK =
"'H"- ONE_b_ZERO_TOK =
"1'b0"- ONE_b_ONE_TOK =
"1'b1"- ONE_b_x_TOK =
"1'bx"- ONE_b_X_TOK =
"1'bX"- ONE_B_ZERO_TOK =
"1'B0"- ONE_B_ONE_TOK =
"1'B1"- ONE_B_x_TOK =
"1'Bx"- ONE_B_X_TOK =
"1'BX"- Q_b_ZERO_TOK =
"'b0"- Q_b_ONE_TOK =
"'b1"- Q_B_ZERO_TOK =
"'B0"- Q_B_ONE_TOK =
"'B1"- WIRE_TOK =
"wire"- TRI_TOK =
"tri"- TRI1_TOK =
"tri1"- SUPPLY0_TOK =
"supply0"- WAND_TOK =
"wand"- TRIAND_TOK =
"triand"- TRI0_TOK =
"tri0"- SUPPLY1_TOK =
"supply1"- WOR_TOK =
"wor"- TRIOR_TOK =
"trior"- TRIREG_TOK =
"trireg"- SMALL_TOK =
"small"- MEDIUM_TOK =
"medium"- LARGE_TOK =
"large"- STRONG0_TOK =
"strong0"- PULL0_TOK =
"pull0"- WEAK0_TOK =
"weak0"- HIGHZ0_TOK =
"highz0"- STRONG1_TOK =
"strong1"- PULL1_TOK =
"pull1"- WEAK1_TOK =
"weak1"- HIGHZ1_TOK =
"highz1"- GATE_AND_TOK =
"and"- GATE_NAND_TOK =
"nand"- GATE_OR_TOK =
"or"- GATE_NOR_TOK =
"nor"- GATE_XOR_TOK =
"xor"- GATE_XNOR_TOK =
"xnor"- GATE_BUF_TOK =
"buf"- GATE_BUFIF0_TOK =
"bufif0"- GATE_BUFIF1_TOK =
"bufif1"- GATE_NOT_TOK =
"not"- GATE_NOTIF0_TOK =
"notif0"- GATE_NOTIF1_TOK =
"notif1"- GATE_PULLDOWN_TOK =
"pulldown"- GATE_PULLUP_TOK =
"pullup"- GATE_NMOS_TOK =
"nmos"- GATE_RNMOS_TOK =
"rnmos"- GATE_PMOS_TOK =
"pmos"- GATE_RPMOS_TOK =
"rpmos"- GATE_CMOS_TOK =
"cmos"- GATE_RCMOS_TOK =
"rcmos"- GATE_TRAN_TOK =
"tran"- GATE_RTRAN_TOK =
"rtran"- GATE_TRANIF0_TOK =
"tranif0"- GATE_RTRANIF0_TOK =
"rtranif0"- GATE_TRANIF1_TOK =
"tranif1"- GATE_RTRANIF1_TOK =
"rtranif1"- ZERO_ONE_TOK =
"01"- ONE_ZERO_TOK =
"10"- ZERO_X_TOK =
"0x"- X_ONE_TOK =
"x1"- ONE_X_TOK =
"1x"- X_ZERO_TOK =
"x0"- POSEDGE_TOK =
"posedge"- NEGEDGE_TOK =
"negedge"- EVENT_OR_TOK =
"or"- EQUAL_TOK =
"="- ASSIGN_ARROW_TEX =
"<="- EQUAL_EQUAL_TOK =
"=="- EQUAL_EQUAL_EQUAL_TOK =
"==="- NOT_EQUAL_TOK =
"!="- NOT_EQUAL_EQUAL_TOK =
"!=="- INFERIOR_TOK =
"<"- SUPERIOR_TOK =
">"- INFERIOR_EQUAL_TOK =
"<="- SUPERIOR_EQUAL_TOK =
">="- AND_AND_TOK =
"&&"- OR_OR_TOK =
"||"- NOT_TOK =
"!"- AND_AND_AND_TOK =
"&&&"- ADD_TOK =
"+"- SUB_TOK =
"-"- MUL_TOK =
"*"- DIV_TOK =
"/"- MOD_TOK =
"%"- POWER_TOK =
"**"- AND_TOK =
"&"- OR_TOK =
"|"- XOR_TOK =
"^"- XOR_TILDE_TOK =
"^~"- RIGHT_SHIFT_TOK =
">>"- LEFT_SHIFT_TOK =
"<<"- RIGHT_ASHIFT_TOK =
">>>"- LEFT_ASHIFT_TOK =
"<<<"- TILDE_TOK =
"~"- TILDE_AND_TOK =
"~&"- XOR_OR_TOK =
"^|"- TILDE_XOR_TOK =
"~^"- TILDE_OR_TOK =
"~|"- SHORT_COMMENT_REX =
/[^\n]*/- LONG_COMMENT_REX =
/([^\*]\/|\*[^\/]|[^\/\*])*/- COMMENT_SPACE_REX =
Comments and spaces with capture in one regular expression
/((?:(?:\/\/[^\n]*\n)|(?:\/\*(?:[^\*]\/|\*[^\/]|[^\/\*])*\*\/)|\s)*)/- S =
Shortcut for combining with other regex
COMMENT_SPACE_REX.source
- COMMA_REX =
/\G#{S}(,)/- SEMICOLON_REX =
/\G#{S}(;)/- COLON_REX =
/\G#{S}(:)/- OPEN_PAR_REX =
/\G#{S}(\()/- CLOSE_PAR_REX =
/\G#{S}(\))/- OPEN_BRA_REX =
/\G#{S}(\[)/- CLOSE_BRA_REX =
/\G#{S}(\])/- OPEN_CUR_REX =
/\G#{S}(\{)/- CLOSE_CUR_REX =
/\G#{S}(\})/- SHARP_REX =
/\G#{S}(#)/- AT_REX =
/\G#{S}(@)/- DOT_REX =
/\G#{S}(\.)/- EE_REX =
/\G#{S}(E)/- Ee_REX =
/\G#{S}(e)/- SLASH_REX =
/\G#{S}(\/)/- SLASH_SLASH_REX =
/\G#{S}(\/\/)/- SLASH_ASTERISK_REX =
/\G#{S}(\/\*)/- ASTERISK_SLASH_REX =
/\G#{S}(\*\/)/- EOL_REX =
/\G#{S}(\n)/- MODULE_REX =
/\G#{S}(module)/- MACROMODULE_REX =
/\G#{S}(macromodule)/- ENDMODULE_REX =
/\G#{S}(endmodule)/- PRIMITIVE_REX =
/\G#{S}(primitive)/- ENDPRIMITIVE_REX =
/\G#{S}(endprimitive)/- TASK_REX =
/\G#{S}(task)/- ENDTASK_REX =
/\G#{S}(endtask)/- FUNCTION_REX =
/\G#{S}(function)/- ENDFUNCTION_REX =
/\G#{S}(endfunction)/- TABLE_REX =
/\G#{S}(table)/- ENDTABLE_REX =
/\G#{S}(endtable)/- SPECIFY_REX =
/\G#{S}(specify)/- ENDSPECIFY_REX =
/\G#{S}(endspecify)/- INPUT_REX =
/\G#{S}(input)/- OUTPUT_REX =
/\G#{S}(output)/- INOUT_REX =
/\G#{S}(inout)/- INITIAL_REX =
/\G#{S}(initial)/- SPECPARAM_REX =
/\G#{S}(specparam)/- IF_REX =
/\G#{S}(if)/- ELSE_REX =
/\G#{S}(else)/- CASE_REX =
/\G#{S}(case)/- CASEZ_REX =
/\G#{S}(casez)/- CASEX_REX =
/\G#{S}(casex)/- ENDCASE_REX =
/\G#{S}(endcase)/- FOREVER_REX =
/\G#{S}(forever)/- REPEAT_REX =
/\G#{S}(repeat)/- WHILE_REX =
/\G#{S}(while)/- FOR_REX =
/\G#{S}(for)/- WAIT_REX =
/\G#{S}(wait)/- RIGHT_ARROW_REX =
/\G#{S}(->)/- DISABLE_REX =
/\G#{S}(disable)/- ASSIGN_REX =
/\G#{S}(assign)/- DEASSIGN_REX =
/\G#{S}(deassign)/- FORCE_REX =
/\G#{S}(force)/- RELEASE_REX =
/\G#{S}(release)/- ALWAYS_REX =
/\G#{S}(always)/- DEFAULT_REX =
/\G#{S}(default)/- BEGIN_REX =
/\G#{S}(begin)/- END_REX =
/\G#{S}(end)/- FORK_REX =
/\G#{S}(fork)/- JOIN_REX =
/\G#{S}(join)/- SIGNED_REX =
/\G#{S}(signed)/- REG_REX =
/\G#{S}(reg)/- TIME_REX =
/\G#{S}(time)/- INTEGER_REX =
/\G#{S}(integer)/- REAL_REX =
/\G#{S}(real)/- EVENT_REX =
/\G#{S}(event)/- DEFPARAM_REX =
/\G#{S}(defparam)/- PARAMETER_REX =
/\G#{S}(parameter|localparam)/- SCALARED_REX =
/\G#{S}(scalared)/- VECTORED_REX =
/\G#{S}(vectored)/- SETUP_REX =
/\G#{S}($setup)/- HOLD_REX =
/\G#{S}($hold)/- PERIOD_REX =
/\G#{S}($period)/- WIDTH_REX =
/\G#{S}($width)/- SKEW_REX =
/\G#{S}($skew)/- RECOVERY_REX =
/\G#{S}($recovery)/- SETUPHOLD_REX =
/\G#{S}($setuphold)/- HYPHEN_REX =
/\G#{S}(-)/- ZERO_REX =
/\G#{S}(0)/- ONE_REX =
/\G#{S}(1)/- Xx_REX =
/\G#{S}(x)/- XX_REX =
/\G#{S}(X)/- Bb_REX =
/\G#{S}(b)/- BB_REX =
/\G#{S}(B)/- QUESTION_REX =
/\G#{S}(\?)/- Rr_REX =
/\G#{S}(r)/- RR_REX =
/\G#{S}(R)/- Ff_REX =
/\G#{S}(f)/- FF_REX =
/\G#{S}(F)/- Pp_REX =
/\G#{S}(p)/- PP_REX =
/\G#{S}(P)/- Nn_REX =
/\G#{S}(n)/- NN_REX =
/\G#{S}(N)/- ASTERISK_REX =
/\G#{S}(\*)/- Q_b_REX =
/\G#{S}('b)/- Q_B_REX =
/\G#{S}('B)/- Q_o_REX =
/\G#{S}('o)/- Q_O_REX =
/\G#{S}('O)/- Q_d_REX =
/\G#{S}('d)/- Q_D_REX =
/\G#{S}('D)/- Q_h_REX =
/\G#{S}('h)/- Q_H_REX =
/\G#{S}('H)/- ONE_b_ZERO_REX =
/\G#{S}(1'b0)/- ONE_b_ONE_REX =
/\G#{S}(1'b1)/- ONE_b_x_REX =
/\G#{S}(1'bx)/- ONE_b_X_REX =
/\G#{S}(1'bX)/- ONE_B_ZERO_REX =
/\G#{S}(1'B0)/- ONE_B_ONE_REX =
/\G#{S}(1'B1)/- ONE_B_x_REX =
/\G#{S}(1'Bx)/- ONE_B_X_REX =
/\G#{S}(1'BX)/- Q_b_ZERO_REX =
/\G#{S}('b0)/- Q_b_ONE_REX =
/\G#{S}('b1)/- Q_B_ZERO_REX =
/\G#{S}('B0)/- Q_B_ONE_REX =
/\G#{S}('B1)/- WIRE_REX =
/\G#{S}(wire)/- TRI_REX =
/\G#{S}(tri)/- TRI1_REX =
/\G#{S}(tri1)/- SUPPLY0_REX =
/\G#{S}(supply0)/- WAND_REX =
/\G#{S}(wand)/- TRIAND_REX =
/\G#{S}(triand)/- TRI0_REX =
/\G#{S}(tri0)/- SUPPLY1_REX =
/\G#{S}(supply1)/- WOR_REX =
/\G#{S}(wor)/- TRIOR_REX =
/\G#{S}(trior)/- TRIREG_REX =
/\G#{S}(trireg)/- SMALL_REX =
/\G#{S}(small)/- MEDIUM_REX =
/\G#{S}(medium)/- LARGE_REX =
/\G#{S}(large)/- STRONG0_REX =
/\G#{S}(strong0)/- PULL0_REX =
/\G#{S}(pull0)/- WEAK0_REX =
/\G#{S}(weak0)/- HIGHZ0_REX =
/\G#{S}(highz0)/- STRONG1_REX =
/\G#{S}(strong1)/- PULL1_REX =
/\G#{S}(pull1)/- WEAK1_REX =
/\G#{S}(weak1)/- HIGHZ1_REX =
/\G#{S}(highz1)/- GATE_AND_REX =
/\G#{S}(and)/- GATE_NAND_REX =
/\G#{S}(nand)/- GATE_OR_REX =
/\G#{S}(or)/- GATE_NOR_REX =
/\G#{S}(nor)/- GATE_XOR_REX =
/\G#{S}(xor)/- GATE_XNOR_REX =
/\G#{S}(xnor)/- GATE_BUF_REX =
/\G#{S}(buf)/- GATE_NBUF_REX =
/\G#{S}(nbuf)/- GATE_NOT_REX =
/\G#{S}(not)/- GATE_NOTIF0_REX =
/\G#{S}(notif0)/- GATE_NOTIF1_REX =
/\G#{S}(notif1)/- GATE_PULLDOWN_REX =
/\G#{S}(pulldown)/- GATE_PULLUP_REX =
/\G#{S}(pullup)/- GATE_NMOS_REX =
/\G#{S}(nmos)/- GATE_RNMOS_REX =
/\G#{S}(rnmos)/- GATE_PMOS_REX =
/\G#{S}(pmos)/- GATE_RPMOS_REX =
/\G#{S}(rpmos)/- GATE_CMOS_REX =
/\G#{S}(cmos)/- GATE_RCMOS_REX =
/\G#{S}(rcmos)/- GATE_TRAN_REX =
/\G#{S}(tran)/- GATE_RTRAN_REX =
/\G#{S}(rtran)/- GATE_TRANIF0_REX =
/\G#{S}(tranif0)/- GATE_RTRANIF0_REX =
/\G#{S}(rtranif0)/- GATE_TRANIF1_REX =
/\G#{S}(tranif1)/- GATE_RTRANIF1_REX =
/\G#{S}(rtranif1)/- ZERO_ONE_REX =
/\G#{S}(01)/- ONE_ZERO_REX =
/\G#{S}(10)/- ZERO_X_REX =
/\G#{S}(0x)/- X_ONE_REX =
/\G#{S}(x1)/- ONE_X_REX =
/\G#{S}(1x)/- X_ZERO_REX =
/\G#{S}(x0)/- POSEDGE_REX =
/\G#{S}(posedge)/- NEGEDGE_REX =
/\G#{S}(negedge)/- EVENT_OR_REX =
/\G#{S}(or)/- EQUAL_REX =
/\G#{S}(=)/- ASSIGN_ARROW_REX =
/\G#{S}(<=)/- EQUAL_EQUAL_REX =
/\G#{S}(==)/- EQUAL_EQUAL_EQUAL_REX =
/\G#{S}(===)/- NOT_EQUAL_REX =
/\G#{S}(!=)/- NOT_EQUAL_EQUAL_REX =
/\G#{S}(!==)/- INFERIOR_REX =
/\G#{S}(<)/- SUPERIOR_REX =
/\G#{S}(>)/- INFERIOR_EQUAL_REX =
/\G#{S}(<=)/- SUPERIOR_EQUAL_REX =
/\G#{S}(>=)/- AND_AND_REX =
/\G#{S}(&&)/- OR_OR_REX =
/\G#{S}(\|\|)/- NOT_REX =
/\G#{S}(!)/- AND_AND_AND_REX =
/\G#{S}(&&&)/- ADD_REX =
/\G#{S}(\+)/- SUB_REX =
/\G#{S}(-)/- MUL_REX =
/\G#{S}(\*)/- DIV_REX =
/\G#{S}(\/)/- MOD_REX =
/\G#{S}(%)/- POWER_REX =
/\G#{S}(\*\*)/- AND_REX =
/\G#{S}(&)/- OR_REX =
/\G#{S}(\|)/- XOR_REX =
/\G#{S}(\^)/- XOR_TILDE_REX =
/\G#{S}(\^~)/- TILDE_REX =
/\G#{S}(~)/- TILDE_AND_REX =
/\G#{S}(~&)/- XOR_OR_REX =
/\G#{S}(\^|)/- TILDE_XOR_REX =
/\G#{S}(~\^)/- TILDE_OR_REX =
/\G#{S}(~\|)/- IDENTIFIER_REX =
/\G#{S}([_a-zA-Z][_\$0-9a-zA-Z]*)/- SYSTEM_IDENTIFIER_REX =
/\G#{S}(\$[_a-zA-Z][_\$0-9a-zA-Z]*)/- STRING_REX =
/\G#{S}("[^"\n]*")/- MODULE_MACROMODULE_TOKS =
TIME_UNIT_TOKS = [ SECOND_TOK, MILLISECOND_TOK, MICROSECOND_TOK, NANOSECOND_TOK, PICOSECOND_TOK, FENTOSECOND_TOK ] TIME_UNIT_REX = /\G#S(#TIME_UNIT_TOKS.join("|"))/
[ MODULE_TOK, MACROMODULE_TOK ]
- MODULE_MACROMODULE_REX =
/\G#{S}(#{MODULE_MACROMODULE_TOKS.join("|")})/- INIT_VAL_TOKS =
[ ONE_b_ZERO_TOK, ONE_b_ONE_TOK, ONE_b_x_TOK, ONE_b_X_TOK, ONE_B_ZERO_TOK, ONE_B_ONE_TOK, ONE_B_x_TOK, ONE_B_X_TOK, ONE_TOK, ZERO_TOK ]
- INIT_VAL_REX =
/\G#{S}(#{INIT_VAL_TOKS.join("|")})/- OUTPUT_SYMBOL_TOKS =
[ ZERO_TOK, ONE_TOK, Xx_TOK, XX_TOK ]
- OUTPUT_SYMBOL_REX =
/\G#{S}(#{OUTPUT_SYMBOL_TOKS.join("|")})/- LEVEL_SYMBOL_TOKS =
[ ZERO_TOK, ONE_TOK, Xx_TOK, XX_TOK, "\\" + QUESTION_TOK, Bb_TOK, BB_TOK ]
- LEVEL_SYMBOL_REX =
/\G#{S}(#{LEVEL_SYMBOL_TOKS.join("|")})/- EDGE_SYMBOL_TOKS =
[ Rr_TOK, RR_TOK, Ff_TOK, FF_TOK, Pp_TOK, PP_TOK, Nn_TOK, NN_TOK, "\\" + ASTERISK_TOK ]
- EDGE_SYMBOL_REX =
/\G#{S}(#{EDGE_SYMBOL_TOKS.join("|")})/- INTEGER_REAL_TOKS =
[ INTEGER_TOK, REAL_TOK ]
- INTEGER_REAL_REX =
/\G#{S}(#{INTEGER_REAL_TOKS.join("|")})/- NETTYPE_TOKS =
[ WIRE_TOK, TRI_TOK, TRI1_TOK, SUPPLY0_TOK, WAND_TOK, TRIAND_TOK, TRI0_TOK, SUPPLY1_TOK, WOR_TOK, TRIOR_TOK, TRIREG_TOK ]
- NETTYPE_REX =
/\G#{S}(#{NETTYPE_TOKS.join("|")})/- INPUTTYPE_TOKS =
[ WIRE_TOK ]
- INPUTTYPE_REX =
/\G#{S}(#{INPUTTYPE_TOKS.join("|")})/- OUTPUTTYPE_TOKS =
Note: the only difference between OUTPUTTYPE and NETTYPE is that the first one has reg, and the second trireg.
[ WIRE_TOK, TRI_TOK, TRI1_TOK, SUPPLY0_TOK, WAND_TOK, TRIAND_TOK, TRI0_TOK, SUPPLY1_TOK, WOR_TOK, TRIOR_TOK, REG_TOK ]
- OUTPUTTYPE_REX =
/\G#{S}(#{OUTPUTTYPE_TOKS.join("|")})/- INOUTTYPE_TOKS =
[ WIRE_TOK ]
- INOUTTYPE_REX =
/\G#{S}(#{INOUTTYPE_TOKS.join("|")})/- CHARGE_STRENGTH_TOKS =
[ SMALL_TOK, MEDIUM_TOK, LARGE_TOK ]
- CHARGE_STRENGTH_REX =
/\G#{S}(#{CHARGE_STRENGTH_TOKS.join("|")})/- STRENGTH0_TOKS =
[ SUPPLY0_TOK, STRONG0_TOK, PULL0_TOK, WEAK0_TOK, HIGHZ0_TOK ]
- STRENGTH0_REX =
/\G#{S}(#{STRENGTH0_TOKS.join("|")})/- STRENGTH1_TOKS =
[ SUPPLY1_TOK, STRONG1_TOK, PULL1_TOK, WEAK1_TOK, HIGHZ1_TOK ]
- STRENGTH1_REX =
/\G#{S}(#{STRENGTH1_TOKS.join("|")})/- GATETYPE_TOKS =
[ GATE_AND_TOK, GATE_NAND_TOK, GATE_OR_TOK, GATE_NOR_TOK, GATE_XOR_TOK, GATE_XNOR_TOK, GATE_BUF_TOK, GATE_BUFIF0_TOK, GATE_BUFIF1_TOK, GATE_NOT_TOK, GATE_NOTIF0_TOK, GATE_NOTIF1_TOK, GATE_PULLDOWN_TOK, GATE_PULLUP_TOK, GATE_NMOS_TOK, GATE_RNMOS_TOK, GATE_PMOS_TOK, GATE_RPMOS_TOK, GATE_CMOS_TOK, GATE_RCMOS_TOK, GATE_TRAN_TOK, GATE_RTRAN_TOK, GATE_TRANIF0_TOK, GATE_RTRANIF0_TOK, GATE_TRANIF1_TOK, GATE_RTRANIF1_TOK ]
- GATETYPE_REX =
/\G#{S}(#{GATETYPE_TOKS.join("|")})[^_a-zA-Z0-9]/- COMMA_CLOSE_PAR_TOKS =
[ COMMA_TOK, "\\" + CLOSE_PAR_TOK ]
- COMMA_CLOSE_PAR_REX =
/\G#{S}(#{COMMA_CLOSE_PAR_TOKS.join("|")})/- CLOSE_BRA_COLON_TOKS =
[ "\\" + CLOSE_BRA_TOK, COLON_TOK ]
- CLOSE_BRA_COLON_REX =
/\G#{S}(#{CLOSE_BRA_COLON_TOKS.join("|")})/- STATEMENT_TOKS =
[ IF_TOK, CASE_TOK, CASEZ_TOK, CASEX_TOK, FOREVER_TOK, REPEAT_TOK, WHILE_TOK, FOR_TOK, WAIT_TOK, RIGHT_ARROW_TOK, DISABLE_TOK, ASSIGN_TOK, FORCE_TOK, DEASSIGN_TOK, RELEASE_TOK ]
- STATEMENT_REX =
/\G#{S}(#{STATEMENT_TOKS.join("|")})/- SYSTEM_TIMING_TOKS =
[ SETUP_TOK, HOLD_TOK, PERIOD_TOK, WIDTH_TOK, SKEW_TOK, RECOVERY_TOK, SETUPHOLD_TOK ]
- SYSTEM_TIMING_REX =
/\G#{S}(#{SYSTEM_TIMING_TOKS.join("|")})/- POSEDGE_NEGEDGE_TOKS =
[ POSEDGE_TOK, NEGEDGE_TOK ]
- POSEDGE_NEGEDGE_REX =
/\G#{S}(#{POSEDGE_NEGEDGE_TOKS.join("|")})/- EDGE_DESCRIPTOR_TOKS =
[ ZERO_ONE_TOK, ONE_ZERO_TOK, ZERO_X_TOK, X_ONE_TOK, ONE_X_TOK, X_ZERO_TOK ]
- EDGE_DESCRIPTOR_REX =
/\G#{S}(#{EDGE_DESCRIPTOR_TOKS.join("|")})/- SCALAR_TIMING_CHECK_CONDITION_TOKS =
[ EQUAL_EQUAL_TOK, EQUAL_EQUAL_EQUAL_TOK, NOT_EQUAL_TOK, NOT_EQUAL_EQUAL_TOK ]
- SCALAR_TIMING_REX =
/\G#{S}(#{SCALAR_TIMING_CHECK_CONDITION_TOKS.join("|")})/- SCALAR_CONSTANT_TOKS =
[ ONE_b_ZERO_TOK, ONE_b_ONE_TOK, ONE_B_ZERO_TOK, ONE_B_ONE_TOK, Q_b_ZERO_TOK, Q_b_ONE_TOK, Q_B_ZERO_TOK, Q_B_ONE_TOK, ONE_TOK, ZERO_TOK ]
- SCALAR_CONSTANT_REX =
/\G#{S}(#{SCALAR_CONSTANT_TOKS.join("|")})/- POLARITY_OPERATOR_TOKS =
[ "\\" + ADD_TOK, SUB_TOK ]
- POLARITY_OPERATOR_REX =
/\G#{S}(#{POLARITY_OPERATOR_TOKS.join("|")})/- EDGE_IDENTIFIER_TOKS =
[ POSEDGE_TOK, NEGEDGE_TOK ]
- EDGE_IDENTIFIER_REX =
/\G#{S}(#{EDGE_IDENTIFIER_TOKS.join("|")})/- OR_OPERATOR_TOKS =
[ "\\" + OR_TOK, TILDE_TOK + "\\" + OR_TOK ]
- OR_OPERATOR_REX =
/\G#{S}(#{OR_OPERATOR_TOKS.join("|")})[^\|]/- XOR_OPERATOR_TOKS =
[ "\\" + XOR_TOK, TILDE_TOK + "\\" + XOR_TOK ]
- XOR_OPERATOR_REX =
/\G#{S}(#{XOR_OPERATOR_TOKS.join("|")})/- AND_OPERATOR_TOKS =
[ AND_TOK, TILDE_AND_TOK ]
- AND_OPERATOR_REX =
/\G#{S}(#{AND_OPERATOR_TOKS.join("|")})[^&]/- EQUAL_OPERATOR_TOKS =
BEFORE_AND_OPERATOR_TOKS = [
[ EQUAL_EQUAL_TOK, NOT_EQUAL_TOK, EQUAL_EQUAL_EQUAL_TOK, NOT_EQUAL_EQUAL_TOK ]
- EQUAL_OPERATOR_REX =
/\G#{S}(#{EQUAL_OPERATOR_TOKS.join("|")})/- COMPARISON_OPERATOR_TOKS =
[ INFERIOR_EQUAL_TOK, SUPERIOR_EQUAL_TOK, INFERIOR_TOK, SUPERIOR_TOK ]
- COMPARISON_OPERATOR_REX =
/\G#{S}(#{COMPARISON_OPERATOR_TOKS.join("|")})/- SHIFT_OPERATOR_TOKS =
[ LEFT_SHIFT_TOK, RIGHT_SHIFT_TOK, LEFT_ASHIFT_TOK, RIGHT_ASHIFT_TOK ]
- SHIFT_OPERATOR_REX =
/\G#{S}(#{SHIFT_OPERATOR_TOKS.join("|")})/- ADD_OPERATOR_TOKS =
[ "\\" + ADD_TOK, SUB_TOK ]
- ADD_OPERATOR_REX =
/\G#{S}(#{ADD_OPERATOR_TOKS.join("|")})/- MUL_OPERATOR_TOKS =
[ "\\" + MUL_TOK, DIV_TOK, MOD_TOK, "\\" + MUL_TOK + "\\" + MUL_TOK ]
- MUL_OPERATOR_REX =
/\G#{S}(#{MUL_OPERATOR_TOKS.join("|")})/- UNARY_OPERATOR_TOKS =
[ "\\" + ADD_TOK, SUB_TOK, NOT_TOK, TILDE_TOK, AND_TOK, TILDE_AND_TOK, "\\" + OR_TOK, TILDE_TOK + "\\" + OR_TOK, "\\" + XOR_TOK + "\\" + OR_TOK, "\\" + XOR_TOK, TILDE_TOK + "\\" + XOR_TOK ]
- UNARY_OPERATOR_REX =
/\G#{S}(#{UNARY_OPERATOR_TOKS.join("|")})/- BINARY_OPERATOR_TOKS =
[ "\\" + ADD_TOK, SUB_TOK, "\\" + MUL_TOK, "\\" + DIV_TOK, MOD_TOK, EQUAL_EQUAL_TOK, NOT_EQUAL_TOK, EQUAL_EQUAL_EQUAL_TOK, NOT_EQUAL_EQUAL_TOK, AND_AND_TOK, "\\" + OR_TOK + "\\" + OR_TOK, INFERIOR_TOK, INFERIOR_EQUAL_TOK, SUPERIOR_TOK, SUPERIOR_EQUAL_TOK, AND_TOK, "\\" + OR_TOK, "\\" + XOR_TOK, "\\" + XOR_TILDE_TOK, RIGHT_SHIFT_TOK, LEFT_SHIFT_TOK ]
- BINARY_OPERATOR_REX =
/\G#{S}(#{BINARY_OPERATOR_TOKS.join("|")})/- EVENT_OR_COMMA_TOKS =
[ EVENT_OR_TOK, COMMA_TOK ]
- EVENT_OR_COMMA_REX =
/\G#{S}(#{EVENT_OR_COMMA_TOKS.join("|")})/- E_TOKS =
[ EE_TOK, Ee_TOK ]
- E_REX =
/\G#{S}(#{E_TOKS.join("|")})/- DECIMAL_NUMBER_REX =
/\G#{S}([+-]?[0-9][_0-9]*)/- UNSIGNED_NUMBER_REX =
/\G#{S}([_0-9][0-9]*)/- NUMBER_REX =
/\G#{S}([0-9a-fA-FzZxX\?][_0-9a-fA-FzZxX\?]*)/- BASE_TOKS =
[ Q_b_TOK, Q_B_TOK, Q_o_TOK, Q_O_TOK, Q_d_TOK, Q_D_TOK, Q_h_TOK, Q_H_TOK ]
- BASE_REX =
/\G#{S}(#{BASE_TOKS.join("|")})/- KEYWORD_SET =
The set of keywords.
- RULES =
The parsing rules: obtained directly from the BNF description of Verilog Each rule is paired with a hook (that returns an AST node by default) that can be redefined.
{}
- ORIGIN_RULES =
The origin rules (from https://www.verilog.com/VerilogBNF.html) that differs from the ones used in this parser.
{}
Instance Method Summary collapse
- #_BASE_hook(tok) ⇒ Object
- #_BASE_parse ⇒ Object
- #_BINARY_OPERATOR_hook(tok) ⇒ Object
- #_BINARY_OPERATOR_parse ⇒ Object
- #_DECIMAL_NUMBER_hook(tok) ⇒ Object
- #_DECIMAL_NUMBER_parse ⇒ Object
- #_EDGE_SYMBOL_hook(symbol) ⇒ Object
- #_EDGE_SYMBOL_parse ⇒ Object
- #_GATETYPE_hook(type) ⇒ Object
- #_GATETYPE_parse ⇒ Object
- #_IDENTIFIER_hook(tok) ⇒ Object
- #_IDENTIFIER_parse ⇒ Object
- #_LEVEL_SYMBOL_hook(symbol) ⇒ Object
- #_LEVEL_SYMBOL_parse ⇒ Object
- #_NETTYPE_hook(type) ⇒ Object
- #_NETTYPE_parse ⇒ Object
-
#_NULL_hook ⇒ Object
Auth: No parse of NULL, since it is literally nothing.
- #_NUMBER_hook(tok) ⇒ Object
- #_NUMBER_parse(base) ⇒ Object
- #_OUTPUT_SYMBOL_hook(symbol) ⇒ Object
- #_OUTPUT_SYMBOL_parse ⇒ Object
- #_QUESTION_MARK_hook(tok) ⇒ Object
- #_QUESTION_MARK_parse ⇒ Object
- #_STRENGTH0_hook(strength0) ⇒ Object
- #_STRENGTH0_parse ⇒ Object
- #_STRENGTH1_hook(strength1) ⇒ Object
- #_STRENGTH1_parse ⇒ Object
- #_STRING_hook(string) ⇒ Object
- #_STRING_parse ⇒ Object
- #_UNARY_OPERATOR_hook(tok) ⇒ Object
- #_UNARY_OPERATOR_parse ⇒ Object
- #_UNSIGNED_NUMBER_hook(tok) ⇒ Object
- #_UNSIGNED_NUMBER_parse ⇒ Object
-
#add_module_name(name) ⇒ Object
Add a known module name.
- #add_term_hook(mul_terms) ⇒ Object
- #add_term_parse ⇒ Object
-
#add_udp_name(name) ⇒ Object
Add a known UDP name.
- #always_statement_hook(statement) ⇒ Object
- #always_statement_parse ⇒ Object
- #assignment_hook(lvalue, expression) ⇒ Object
- #assignment_parse ⇒ Object
- #bit_and_term_hook(equal_terms) ⇒ Object
- #bit_and_term_parse ⇒ Object
- #bit_or_term_hook(bit_xor_terms) ⇒ Object
- #bit_or_term_parse ⇒ Object
- #bit_xor_term_hook(bit_and_terms) ⇒ Object
- #bit_xor_term_parse ⇒ Object
- #block_declaration_hook(declaration) ⇒ Object
- #block_declaration_parse ⇒ Object
- #blocking_assignment_hook(lvalue, delay_or_event_control, expression) ⇒ Object
- #blocking_assignment_parse ⇒ Object
- #case_item_hook(cas, statement_or_null) ⇒ Object
- #case_item_parse ⇒ Object
- #charge_strength_hook(type) ⇒ Object
- #charge_strength_parse ⇒ Object
- #combinational_entry_hook(level_input_list, output_symbol) ⇒ Object
- #combinational_entry_parse ⇒ Object
- #comment_hook(comment) ⇒ Object
- #comment_parse ⇒ Object
- #comment_text_hook(tok) ⇒ Object
- #comparison_term_hook(shift_terms) ⇒ Object
- #comparison_term_parse ⇒ Object
- #concatenation_hook(expressions) ⇒ Object
- #concatenation_parse ⇒ Object
- #condition_term_hook(logic_or_terms) ⇒ Object
- #condition_term_parse ⇒ Object
- #conditional_port_expression_hook(port_reference__unary_operator, binary_operator, port_reference) ⇒ Object
- #conditional_port_expression_parse ⇒ Object
- #constant_expression_hook(expression) ⇒ Object
- #constant_expression_parse ⇒ Object
- #continuous_assignment_hook(nettype, drive_strength, expandrange, delay, list_of_assignments) ⇒ Object
- #continuous_assignment_parse ⇒ Object
- #controlled_timing_check_event_hook(timing_check_event_control, specify_terminal_descriptor, timing_check_condition) ⇒ Object
- #controlled_timing_check_event_parse ⇒ Object
- #data_source_hook(expression) ⇒ Object
- #data_source_parse ⇒ Object
- #delay_control_hook(number__identifier__mintypmax_expression) ⇒ Object
- #delay_control_parse ⇒ Object
- #delay_hook(number__identifier__mintypmax_expression, mintypmax_expression1, mintypmax_expression2) ⇒ Object
- #delay_or_event_control_hook(base, arg0, arg1) ⇒ Object
- #delay_or_event_control_parse ⇒ Object
- #delay_parse ⇒ Object
- #description_hook(elem) ⇒ Object
- #description_parse ⇒ Object
- #drive_strength_hook(strengthL, strengthR) ⇒ Object
- #drive_strength_parse ⇒ Object
-
#each_origin_rule(&ruby_block) ⇒ Object
Access each origin rule.
-
#each_rule(&ruby_block) ⇒ Object
Access each rule.
- #edge_control_specifier_hook(edge_descriptors) ⇒ Object
- #edge_control_specifier_parse ⇒ Object
- #edge_descriptor_hook(tok) ⇒ Object
- #edge_descriptor_parse ⇒ Object
- #edge_hook(edge) ⇒ Object
- #edge_identifier_hook(tok) ⇒ Object
- #edge_identifier_parse ⇒ Object
- #edge_input_list_hook(level_symbols0, edge, level_symbols1) ⇒ Object
- #edge_input_list_parse ⇒ Object
- #edge_parse ⇒ Object
- #edge_sensitive_path_declaration_hook(expression, edge_identifier, specify_input_terminal_descriptor, tok, specify_output_terminal_descriptor__list_of_path_outputs, polarity_operator, data_source_expression, path_delay_value) ⇒ Object
- #edge_sensitive_path_declaration_parse ⇒ Object
-
#eof? ⇒ Boolean
Tells if the end of file/string is reached (ignores the spaces and comments for this check).
- #equal_term_hook(comparison_terms) ⇒ Object
- #equal_term_parse ⇒ Object
- #event_control_hook(identifier__event_control) ⇒ Object
- #event_control_parse ⇒ Object
- #event_declaration_hook(name_of_events) ⇒ Object
- #event_declaration_parse ⇒ Object
- #event_expression_hook(event_primaries) ⇒ Object
- #event_expression_parse ⇒ Object
- #event_primary_hook(tok__expression, event_expression) ⇒ Object
- #event_primary_parse ⇒ Object
- #expandrange_hook(type, range) ⇒ Object
- #expandrange_parse ⇒ Object
- #expression_hook(string__condition_terms) ⇒ Object
- #expression_parse ⇒ Object
-
#file_error(error, lpos = @state.lpos) ⇒ Object
Generate a file error with origin indicated in +error+.
- #function_call_hook(name_of_function__name_of_system_function, expressions) ⇒ Object
- #function_call_parse ⇒ Object
- #function_hook(range_or_type, name_of_function, tf_declarations, statement) ⇒ Object
- #function_parse ⇒ Object
- #gate_declaration_hook(gatetype, drive_strength, delay, gate_instances) ⇒ Object
- #gate_declaration_parse ⇒ Object
- #gate_instance_hook(name_of_gate_instance, terminals) ⇒ Object
- #gate_instance_parse ⇒ Object
-
#get_token(rex) ⇒ Object
Get the token matching regexp +rex+ if any from current position.
- #identifier_hook(identifiers) ⇒ Object
- #identifier_parse ⇒ Object
- #init_val_hook(val) ⇒ Object
- #init_val_parse ⇒ Object
- #initial_statement_hook(statement) ⇒ Object
- #initial_statement_parse ⇒ Object
-
#initialize ⇒ Parser
constructor
Create a new parser.
- #inout_declaration_hook(type, sign, range, list_of_variables) ⇒ Object
- #inout_declaration_parse ⇒ Object
- #inout_port_declaration_hook(type, sign, range, name_of_variable) ⇒ Object
- #inout_port_declaration_parse ⇒ Object
- #input_declaration_hook(type, sign, range, list_of_variables) ⇒ Object
- #input_declaration_parse ⇒ Object
- #input_identifier_hook(identifier) ⇒ Object
- #input_identifier_parse ⇒ Object
- #input_list_hook(input_list) ⇒ Object
- #input_list_parse ⇒ Object
- #input_port_declaration_hook(type, sign, range, name_of_variable) ⇒ Object
- #input_port_declaration_parse ⇒ Object
- #integer_declaration_hook(list_of_register_variables) ⇒ Object
- #integer_declaration_parse ⇒ Object
- #level_input_list_hook(level_symbols) ⇒ Object
- #level_input_list_parse ⇒ Object
- #level_sensitive_path_declaration_hook(conditional_port_expression, input, polarity_operator, tok, output, path_delay_value) ⇒ Object
- #level_sensitive_path_declaration_parse ⇒ Object
- #list_of_assignments_hook(assignments) ⇒ Object
- #list_of_assignments_parse ⇒ Object
- #list_of_module_connections_hook(connections) ⇒ Object
- #list_of_module_connections_parse ⇒ Object
- #list_of_param_assignments_hook(param_assignments) ⇒ Object
- #list_of_param_assignments_parse ⇒ Object
- #list_of_path_inputs_hook(specify_input_terminal_descriptors) ⇒ Object
- #list_of_path_inputs_parse ⇒ Object
- #list_of_path_outputs_hook(specify_output_terminal_descriptors) ⇒ Object
- #list_of_path_outputs_parse ⇒ Object
- #list_of_ports_hook(ports) ⇒ Object
- #list_of_ports_parse ⇒ Object
- #list_of_register_variables_hook(register_variables) ⇒ Object
- #list_of_register_variables_parse ⇒ Object
- #list_of_variables_hook(name_of_variables) ⇒ Object
- #list_of_variables_parse ⇒ Object
- #logic_and_term_hook(bit_or_terms) ⇒ Object
- #logic_and_term_parse ⇒ Object
- #logic_or_term_hook(logic_and_terms) ⇒ Object
- #logic_or_term_parse ⇒ Object
- #long_comment_hook(comment_text) ⇒ Object
- #long_comment_parse ⇒ Object
- #long_comment_text_parse ⇒ Object
- #lvalue_hook(identifier__concatenation, expression__constant_expression, constant_expression) ⇒ Object
- #lvalue_parse ⇒ Object
- #mintypmax_expression_hook(expression0, expression1, expression2) ⇒ Object
- #mintypmax_expression_parse ⇒ Object
-
#module_hook(name, pre_parameter_declaration, ports, elems) ⇒ Object
,.
- #module_instance_hook(name_of_instance, list_of_module_connections) ⇒ Object
- #module_instance_parse ⇒ Object
- #module_instantiation_hook(name_of_module, parameter_value_assignment, module_instances) ⇒ Object
- #module_instantiation_parse ⇒ Object
- #module_item_hook(item) ⇒ Object
- #module_item_parse ⇒ Object
-
#module_name?(name) ⇒ Boolean
Tells if a name is a known module name.
- #module_parse ⇒ Object
- #module_port_connection_hook(expression) ⇒ Object
- #module_port_connection_parse ⇒ Object
- #mul_term_hook(unary_terms) ⇒ Object
- #mul_term_parse ⇒ Object
- #multiple_concatenation_hook(expression, expressions) ⇒ Object
- #multiple_concatenation_parse ⇒ Object
- #name_of_block_hook(identifier) ⇒ Object
- #name_of_block_parse ⇒ Object
- #name_of_event_hook(identifier) ⇒ Object
- #name_of_event_parse ⇒ Object
- #name_of_function_hook(identifier) ⇒ Object
- #name_of_function_parse ⇒ Object
- #name_of_gate_instance_hook(identifier, range) ⇒ Object
- #name_of_gate_instance_parse ⇒ Object
- #name_of_instance_hook(identifier, range) ⇒ Object
- #name_of_instance_parse ⇒ Object
- #name_of_memory_hook(identifier) ⇒ Object
- #name_of_memory_parse ⇒ Object
- #name_of_module_hook(identifier) ⇒ Object
- #name_of_module_parse ⇒ Object
- #name_of_port_hook(name) ⇒ Object
- #name_of_port_parse ⇒ Object
- #name_of_register_hook(identifier) ⇒ Object
- #name_of_register_parse ⇒ Object
- #name_of_system_function_hook(identifier) ⇒ Object
- #name_of_system_function_parse ⇒ Object
- #name_of_system_task_hook(identifier) ⇒ Object
- #name_of_system_task_parse ⇒ Object
- #name_of_task_hook(name_of_task) ⇒ Object
- #name_of_task_parse ⇒ Object
- #name_of_udp_hook(identifier) ⇒ Object
- #name_of_udp_instance_hook(identifier, range) ⇒ Object
- #name_of_udp_instance_parse ⇒ Object
- #name_of_udp_parse ⇒ Object
- #name_of_variable_hook(identifier) ⇒ Object
- #name_of_variable_parse ⇒ Object
- #named_port_connection_hook(identifier, expression) ⇒ Object
- #named_port_connection_parse ⇒ Object
- #net_declaration_hook(nettype_or_charge_strength, sign, expandrange, delay, list_of_variables_or_list_of_assignments) ⇒ Object
- #net_declaration_parse ⇒ Object
- #next_state_hook(symbol) ⇒ Object
- #next_state_parse ⇒ Object
- #non_blocking_assignment_hook(lvalue, delay_or_event_control, expression) ⇒ Object
- #non_blocking_assignment_parse ⇒ Object
- #notify_register_hook(identifier) ⇒ Object
- #notify_register_parse ⇒ Object
- #number_hook(unsigned_number__decimal_number, base__unsigned_number, decimal_number) ⇒ Object
- #number_parse ⇒ Object
-
#origin_rule(name) ⇒ Object
Get an origin rule by +name+.
- #output_declaration_hook(type, sign, range, list_of_variables) ⇒ Object
- #output_declaration_parse ⇒ Object
- #output_identifier_hook(identifier) ⇒ Object
- #output_identifier_parse ⇒ Object
- #output_port_declaration_hook(type, sign, range, name_of_variable) ⇒ Object
- #output_port_declaration_parse ⇒ Object
- #output_terminal_name_hook(name_of_variable) ⇒ Object
- #output_terminal_name_parse ⇒ Object
- #par_block_hook(statements__name_of_block, block_declarations, statements) ⇒ Object
- #par_block_parse ⇒ Object
- #param_assignment_hook(identifier, constant_expression) ⇒ Object
- #param_assignment_parse ⇒ Object
- #parameter_declaration_hook(list_of_param_assignments) ⇒ Object
- #parameter_declaration_parse ⇒ Object
- #parameter_override_hook(list_of_param_assignments) ⇒ Object
- #parameter_override_parse ⇒ Object
- #parameter_value_assignment_hook(expressions) ⇒ Object
- #parameter_value_assignment_parse ⇒ Object
-
#parse ⇒ Object
Parse the Verilog HDL text.
-
#parse_error(msg, line_txt = nil, lpos = @state.lpos, cpos = @state.cpos, filename = ) ⇒ Object
Generate a parse error with message indicated by +msg+ and possible line text +line_text+, line number +lpos+, column +cpos+ and origin file name +filename+.
- #path_declaration_hook(path_description, path_delay_value) ⇒ Object
- #path_declaration_parse ⇒ Object
- #path_delay_expression_hook(mintypmax_expression) ⇒ Object
- #path_delay_expression_parse ⇒ Object
- #path_delay_value_hook(path_delay_expression0, path_delay_expression1, path_delay_expression2, path_delay_expression3, path_delay_expression4, path_delay_expression5, path_delay_expression6, path_delay_expression7, path_delay_expression8, path_delay_expression9, path_delay_expression10, path_delay_expression11) ⇒ Object
- #path_delay_value_parse ⇒ Object
- #path_description_hook(type, input, output) ⇒ Object
- #path_description_parse ⇒ Object
-
#peek_token(rex) ⇒ Object
Check the token matching regexp +rex+ from current position.
- #polarity_operator_hook(tok) ⇒ Object
- #polarity_operator_parse ⇒ Object
- #port_expression_hook(port_declaration__port_refs) ⇒ Object
- #port_expression_parse ⇒ Object
- #port_hook(port_expression__name_of_port, port_expression) ⇒ Object
- #port_parse ⇒ Object
- #port_reference_hook(name, const0, const1) ⇒ Object
- #port_reference_parse ⇒ Object
- #pre_parameter_declaration_hook(list_of_param_assignments) ⇒ Object
- #pre_parameter_declaration_parse ⇒ Object
-
#preprocess ⇒ Object
Preprocess the Verilog HDL text with directives.
- #primary_hook(base, expression__constant_expression, constant_expression) ⇒ Object
- #primary_parse ⇒ Object
-
#property_hook ⇒ Object
Hook for the properties of the current line.
- #range_hook(constant_expression0, constant_expression1) ⇒ Object
- #range_or_type_hook(range_or_type) ⇒ Object
- #range_or_type_parse ⇒ Object
- #range_parse ⇒ Object
- #real_declaration_hook(list_of_register_variables) ⇒ Object
- #real_declaration_parse ⇒ Object
- #reg_declaration_hook(sign, range, list_of_register_variables) ⇒ Object
- #reg_declaration_parse ⇒ Object
- #register_variable_hook(name, constant_expression1, constant_expression2) ⇒ Object
- #register_variable_parse ⇒ Object
-
#rule(name) ⇒ Object
Get a rule by +name+.
-
#run(text: nil, filename: "", compress: false) ⇒ Object
Runs the full preprocesser and parser for text to parse +text+ and/or origin file named +filename+.
- #scalar_constant_hook(tok) ⇒ Object
- #scalar_constant_parse ⇒ Object
- #scalar_event_expression_hook(scalar_event_expression) ⇒ Object
- #scalar_event_expression_parse ⇒ Object
- #scalar_expression_hook(expression) ⇒ Object
- #scalar_expression_parse ⇒ Object
- #scalar_timing_check_condition_hook(scalar_expression__tok, scalar_expression, scalar_constant) ⇒ Object
- #scalar_timing_check_condition_parse ⇒ Object
- #sdpd_conditional_expression_hook(unary_operator__expression, expression__binary_operator, expression) ⇒ Object
- #sdpd_conditional_expression_parse ⇒ Object
- #sdpd_hook(sdpd_conditional_expression, path_description, path_delay_value) ⇒ Object
- #sdpd_parse ⇒ Object
- #seq_block_hook(name_of_block, block_declarations, statements) ⇒ Object
- #seq_block_parse ⇒ Object
- #sequential_entry_hook(input_list, _state, next_state) ⇒ Object
- #sequential_entry_parse ⇒ Object
-
#setup(text: nil, filename: "", compress: false) ⇒ Object
Set up the parser with text to parse +text+ and/or origin file named +filename+.
- #shift_term_hook(add_terms) ⇒ Object
- #shift_term_parse ⇒ Object
- #short_comment_hook(comment_text) ⇒ Object
- #short_comment_parse ⇒ Object
- #short_comment_text_parse ⇒ Object
- #source_text_hook(elems) ⇒ Object
- #source_text_parse ⇒ Object
- #specify_block_hook(specify_items) ⇒ Object
- #specify_block_parse ⇒ Object
- #specify_input_terminal_descriptor_hook(input_identifier, constant_expression, constant_expression2) ⇒ Object
- #specify_input_terminal_descriptor_parse ⇒ Object
- #specify_item_hook(declaration) ⇒ Object
- #specify_item_parse ⇒ Object
- #specify_output_terminal_descriptor_hook(output_identifier, constant_expression, constant_expression2) ⇒ Object
- #specify_output_terminal_descriptor_parse ⇒ Object
- #specify_terminal_descriptor_hook(specify_terminal_descriptor) ⇒ Object
- #specify_terminal_descriptor_parse ⇒ Object
- #specparam_declaration_hook(list_of_param_assignments) ⇒ Object
- #specparam_declaration_parse ⇒ Object
-
#state ⇒ Object
Get a copy of the current state.
-
#state=(state) ⇒ Object
Sets the current state.
- #state_hook(level_symbol) ⇒ Object
- #state_parse ⇒ Object
- #statement_hook(base, arg0, arg1, arg2, arg3) ⇒ Object
- #statement_or_null_hook(statement) ⇒ Object
- #statement_or_null_parse ⇒ Object
- #statement_parse ⇒ Object
- #system_identifier_hook(tok) ⇒ Object
- #system_identifier_parse ⇒ Object
- #system_task_enable_hook(name_of_system_task, expressions) ⇒ Object
- #system_task_enable_parse ⇒ Object
- #system_timing_check_hook(tok, arg0, arg1, arg2, arg3, arg4) ⇒ Object
- #system_timing_check_parse ⇒ Object
- #table_definition_hook(table_entries) ⇒ Object
- #table_definition_parse ⇒ Object
- #table_entries_hook(entries) ⇒ Object
- #table_entries_parse ⇒ Object
- #task_enable_hook(name_of_task, expressions) ⇒ Object
- #task_enable_parse ⇒ Object
- #task_hook(name_of_task, tf_declaration, statement_or_null) ⇒ Object
- #task_parse ⇒ Object
- #terminal_hook(terminal) ⇒ Object
- #terminal_parse ⇒ Object
- #tf_declaration_hook(declaration) ⇒ Object
- #tf_declaration_parse ⇒ Object
- #time_declaration_hook(list_of_register_variables) ⇒ Object
- #time_declaration_parse ⇒ Object
- #timing_check_condition_hook(scalar_timing_check_condition) ⇒ Object
- #timing_check_condition_parse ⇒ Object
- #timing_check_event_control_hook(tok__edge_control_specifier) ⇒ Object
- #timing_check_event_control_parse ⇒ Object
- #timing_check_event_hook(timing_check_event_control, specify_terminal_descriptor, timing_check_condition) ⇒ Object
- #timing_check_event_parse ⇒ Object
- #timing_check_list_hook(expression) ⇒ Object
- #timing_check_list_parse ⇒ Object
- #udp_declaration_hook(declaration) ⇒ Object
- #udp_declaration_parse ⇒ Object
- #udp_hook(name, name_of_variables, udp_declarations, udp_initial_statement, table_definition) ⇒ Object
- #udp_initial_statement_hook(output_terminal_name, init_val) ⇒ Object
- #udp_initial_statement_parse ⇒ Object
- #udp_instance_hook(name_of_udp_instance, terminals) ⇒ Object
- #udp_instance_parse ⇒ Object
- #udp_instantiation_hook(name_of_udp, drive_strength, delay, udp_instances) ⇒ Object
- #udp_instantiation_parse ⇒ Object
-
#udp_name?(name) ⇒ Boolean
Tells if a name is a known UDP name.
- #udp_parse ⇒ Object
Constructor Details
#initialize ⇒ Parser
Create a new parser.
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# File 'lib/HDLRuby/verilog_parser.rb', line 128 def initialize # Create the parse state. # It includes: # +compress+: is the compressed version of the AST to generate. # +text+: the text to parse # +filename+: the origin file name (if any) # +lprop+: the properties of each line. @state = Struct.new(:compress, :text, :filename, :path, :lprop, :index, :lpos, :cpos).new(false,"","",[],0,0) # Create the list of known module names. @module_names = [] # Create the list of known UDP names. @udp_names = [] end |
Instance Method Details
#_BASE_hook(tok) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6722 def _BASE_hook(tok) return AST[:BASE, tok, self.property_hook] end |
#_BASE_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6714 def _BASE_parse tok = self.get_token(BASE_REX) if tok then return _BASE_hook(tok) end return nil end |
#_BINARY_OPERATOR_hook(tok) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6440 def _BINARY_OPERATOR_hook(tok) return AST[:BINARY_OPERATOR, tok, self.property_hook ] end |
#_BINARY_OPERATOR_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6432 def _BINARY_OPERATOR_parse tok = self.get_token(BINARY_OPERATOR_REX) if tok then return self._BINARY_OPERATOR_hook(tok) end return nil end |
#_DECIMAL_NUMBER_hook(tok) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6626 def _DECIMAL_NUMBER_hook(tok) return AST[:DECIMAL_NUMBER, tok, self.property_hook ] end |
#_DECIMAL_NUMBER_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6618 def _DECIMAL_NUMBER_parse tok = self.get_token(DECIMAL_NUMBER_REX) if tok then return self._DECIMAL_NUMBER_hook(tok) end return nil end |
#_EDGE_SYMBOL_hook(symbol) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2352 def _EDGE_SYMBOL_hook(symbol) return AST[:EDGE_SYMBOL, symbol, self.property_hook ] end |
#_EDGE_SYMBOL_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2346 def _EDGE_SYMBOL_parse symbol = self.get_token(EDGE_SYMBOL_REX) return nil unless symbol return self._EDGE_SYMBOL_hook(symbol) end |
#_GATETYPE_hook(type) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3363 def _GATETYPE_hook(type) return AST[:GATETYPE, type, self.property_hook ] end |
#_GATETYPE_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3355 def _GATETYPE_parse type = self.get_token(GATETYPE_REX) unless type return nil end return _GATETYPE_hook(type) end |
#_IDENTIFIER_hook(tok) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 7067 def _IDENTIFIER_hook(tok) return AST[:_IDENTIFIER, tok, self.property_hook ] end |
#_IDENTIFIER_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 7054 def _IDENTIFIER_parse parse_state = self.state tok = self.get_token(IDENTIFIER_REX) # puts "tok=#{tok}" return nil unless tok if KEYWORD_SET.include?(tok) then # An identifier cannot be a keyword! self.state = parse_state return nil end return self._IDENTIFIER_hook(tok) end |
#_LEVEL_SYMBOL_hook(symbol) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2336 def _LEVEL_SYMBOL_hook(symbol) return AST[:LEVEL_SYMBOL, symbol, self.property_hook ] end |
#_LEVEL_SYMBOL_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2330 def _LEVEL_SYMBOL_parse symbol = self.get_token(LEVEL_SYMBOL_REX) return nil unless symbol return self._LEVEL_SYMBOL_hook(symbol) end |
#_NETTYPE_hook(type) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2794 def _NETTYPE_hook(type) return AST[:NETTYPE, type, self.property_hook ] end |
#_NETTYPE_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2787 def _NETTYPE_parse type = self.get_token(NETTYPE_REX) return nil unless type # self.parse_error("one of [#{NETTYPE_TOKS.join(",")}] expected") unless type return self._NETTYPE_hook(type) end |
#_NULL_hook ⇒ Object
Auth: No parse of NULL, since it is literally nothing.
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# File 'lib/HDLRuby/verilog_parser.rb', line 3804 def _NULL_hook return AST[:NULL, self.property_hook ] end |
#_NUMBER_hook(tok) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6704 def _NUMBER_hook(tok) return AST[:NUMBER, tok, self.property_hook ] end |
#_NUMBER_parse(base) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6673 def _NUMBER_parse(base) tok = self.get_token(NUMBER_REX) case(base) when Q_b_TOK, Q_B_TOK # Binary case. if tok =~ /^[0-1xXzZ\?][_0-1xXzZ\?]*$/ then return self._NUMBER_hook(tok) end self.parse_error("malformed number") when Q_o_TOK, Q_O_TOK # Octal case. if tok =~ /^[0-7xXzZ\?][_0-7xXzZ\?]*$/ then return self._NUMBER_hook(tok) end self.parse_error("malformed number") when Q_d_TOK, Q_D_TOK # Decimal case. if tok =~ /^[0-9xXzZ\?][_0-9xXzZ\?]*$/ then return self._NUMBER_hook(tok) end self.parse_error("malformed number") when Q_h_TOK, Q_H_TOK # hexecimal case. if tok =~ /^[0-9a-fA-FxXzZ\?][_0-9a-fA-FxXzZ\?]*$/ then return self._NUMBER_hook(tok) end self.parse_error("malformed number") end raise "Internal error: should not be there!" end |
#_OUTPUT_SYMBOL_hook(symbol) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2320 def _OUTPUT_SYMBOL_hook(symbol) return AST[:OUTPUT_SYMBOL, symbol, self.property_hook ] end |
#_OUTPUT_SYMBOL_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2314 def _OUTPUT_SYMBOL_parse symbol = self.get_token(OUTPUT_SYMBOL_REX) return nil unless symbol return self._OUTPUT_SYMBOL_hook(symbol) end |
#_QUESTION_MARK_hook(tok) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6456 def _QUESTION_MARK_hook(tok) return AST[:QUESTION_MARK, tok, self.property_hook ] end |
#_QUESTION_MARK_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6449 def _QUESTION_MARK_parse if self.get_token(QUESTION_REX) then return _QUESTION_MARK_hook(QUESTION_TOK) end return nil end |
#_STRENGTH0_hook(strength0) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3242 def _STRENGTH0_hook(strength0) return AST[:STRENGTH0, strength0, self.property_hook ] end |
#_STRENGTH0_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3234 def _STRENGTH0_parse strength0 = self.get_token(STRENGTH0_REX) unless strength0 return nil end return _STRENGTH0_hook(strength0) end |
#_STRENGTH1_hook(strength1) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3260 def _STRENGTH1_hook(strength1) return AST[:STRENGTH1, strength1, self.property_hook ] end |
#_STRENGTH1_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3252 def _STRENGTH1_parse strength1 = self.get_token(STRENGTH1_REX) unless strength1 return nil end return _STRENGTH1_hook(strength1) end |
#_STRING_hook(string) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6473 def _STRING_hook(string) return AST[:STRING, string, self.property_hook ] end |
#_STRING_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6465 def _STRING_parse string = self.get_token(STRING_REX) if string then return _STRING_hook(string) end return nil end |
#_UNARY_OPERATOR_hook(tok) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6422 def _UNARY_OPERATOR_hook(tok) return AST[:UNARY_OPERATOR, tok, self.property_hook ] end |
#_UNARY_OPERATOR_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6414 def _UNARY_OPERATOR_parse tok = self.get_token(UNARY_OPERATOR_REX) if tok then return self._UNARY_OPERATOR_hook(tok) end return nil end |
#_UNSIGNED_NUMBER_hook(tok) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6645 def _UNSIGNED_NUMBER_hook(tok) return AST[:UNSIGNED_NUMBER, tok, self.property_hook ] end |
#_UNSIGNED_NUMBER_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6637 def _UNSIGNED_NUMBER_parse tok = self.get_token(UNSIGNED_NUMBER_REX) if tok then return self._UNSIGNED_NUMBER_hook(tok) end return nil end |
#add_module_name(name) ⇒ Object
Add a known module name.
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# File 'lib/HDLRuby/verilog_parser.rb', line 609 def add_module_name(name) @module_names << name.to_s end |
#add_term_hook(mul_terms) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6368 def add_term_hook(mul_terms) if self.state.compress and mul_terms.size == 1 then return mul_terms[0] else return AST[:and_term, mul_terms, self.property_hook ] end end |
#add_term_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6351 def add_term_parse # puts "add_term_parse" cur_mul_term = self.mul_term_parse return nil unless cur_mul_term mul_terms = [ cur_mul_term ] tok = nil loop do tok = self.get_token(MUL_OPERATOR_REX) break unless tok mul_terms << tok cur_mul_term = self.mul_term_parse self.parse_error("expression expected") unless cur_mul_term mul_terms << cur_mul_term end return add_term_hook(mul_terms) end |
#add_udp_name(name) ⇒ Object
Add a known UDP name.
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# File 'lib/HDLRuby/verilog_parser.rb', line 614 def add_udp_name(name) @udp_names << name.to_s end |
#always_statement_hook(statement) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3866 def always_statement_hook(statement) return AST[:always_statement, statement, self.property_hook ] end |
#always_statement_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3859 def always_statement_parse return nil unless self.get_token(ALWAYS_REX) statement = self.statement_parse self.parse_error("statement expected") unless statement return self.always_statement_hook(statement) end |
#assignment_hook(lvalue, expression) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 4078 def assignment_hook(lvalue,expression) return AST[:assignment, lvalue,expression, self.property_hook ] end |
#assignment_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 4062 def assignment_parse parse_state = self.state lvalue = self.lvalue_parse unless lvalue then self.state = parse_state return nil end unless self.get_token(EQUAL_REX) then self.state = parse_state return nil end expression = self.expression_parse self.parse_error("expression expected") unless expression return self.assignment_hook(lvalue,expression) end |
#bit_and_term_hook(equal_terms) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6236 def bit_and_term_hook(equal_terms) if self.state.compress and equal_terms.size == 1 then return equal_terms[0] else return AST[:bit_and_term, equal_terms, self.property_hook ] end end |
#bit_and_term_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6219 def bit_and_term_parse # puts "bit_and_term_parse" cur_equal_term = self.equal_term_parse return nil unless cur_equal_term equal_terms = [ cur_equal_term ] tok = nil loop do tok = self.get_token(EQUAL_OPERATOR_REX) break unless tok equal_terms << tok cur_equal_term = self.equal_term_parse self.parse_error("expression expected") unless cur_equal_term equal_terms << cur_equal_term end return bit_and_term_hook(equal_terms) end |
#bit_or_term_hook(bit_xor_terms) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6169 def bit_or_term_hook(bit_xor_terms) if self.state.compress and bit_xor_terms.size == 1 then return bit_xor_terms[0] else return AST[:bit_or_term, bit_xor_terms, self.property_hook ] end end |
#bit_or_term_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6152 def bit_or_term_parse # puts "bit_or_term_parse" cur_bit_xor_term = self.bit_xor_term_parse return nil unless cur_bit_xor_term bit_xor_terms = [ cur_bit_xor_term ] tok = nil loop do tok = self.get_token(XOR_OPERATOR_REX) break unless tok bit_xor_terms << tok cur_bit_xor_term = self.bit_xor_term_parse self.parse_error("expression expected") unless cur_bit_xor_term bit_xor_terms << cur_bit_xor_term end return bit_or_term_hook(bit_xor_terms) end |
#bit_xor_term_hook(bit_and_terms) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6203 def bit_xor_term_hook(bit_and_terms) if self.state.compress and bit_and_terms.size == 1 then return bit_and_terms[0] else return AST[:bit_xor_term, bit_and_terms, self.property_hook ] end end |
#bit_xor_term_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6185 def bit_xor_term_parse # puts "bit_xor_term_parse" parse_state = self.state cur_bit_and_term = self.bit_and_term_parse return nil unless cur_bit_and_term bit_and_terms = [ cur_bit_and_term ] tok = nil loop do tok = self.get_token(AND_OPERATOR_REX) break unless tok bit_and_terms << tok cur_bit_and_term = self.bit_and_term_parse self.parse_error("expression expected") unless cur_bit_and_term bit_and_terms << cur_bit_and_term end return bit_xor_term_hook(bit_and_terms) end |
#block_declaration_hook(declaration) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 4379 def block_declaration_hook(declaration) if self.state.compress then return declaration else return AST[:block_declaration, declaration, self.property_hook ] end end |
#block_declaration_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 4351 def block_declaration_parse parameter_declaration = self.parameter_declaration_parse if parameter_declaration then return self.block_declaration_hook(parameter_declaration) end reg_declaration = self.reg_declaration_parse if reg_declaration then return self.block_declaration_hook(reg_declaration) end integer_declaration = self.integer_declaration_parse if integer_declaration then return self.block_declaration_hook(integer_declaration) end real_declaration = self.real_declaration_parse if real_declaration then return self.block_declaration_hook(real_declaration) end time_declaration = self.time_declaration_parse if time_declaration then return self.block_declaration_hook(time_declaration) end event_declaration = self.event_declaration_parse if event_declaration then return self.block_declaration_hook(event_declaration) end return nil end |
#blocking_assignment_hook(lvalue, delay_or_event_control, expression) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 4107 def blocking_assignment_hook(lvalue, delay_or_event_control, expression) return AST[:blocking_assignment, lvalue,delay_or_event_control,expression, self.property_hook ] end |
#blocking_assignment_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 4089 def blocking_assignment_parse parse_state = self.state lvalue = self.lvalue_parse return nil unless lvalue unless self.get_token(EQUAL_REX) then self.state = parse_state return nil end delay_or_event_control = self.delay_or_event_control_parse expression = self.expression_parse unless expression then self.state = parse_state return nil end return self.blocking_assignment_hook(lvalue,delay_or_event_control, expression) end |
#case_item_hook(cas, statement_or_null) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 4220 def case_item_hook(cas, statement_or_null) return AST[:case_item, cas,statement_or_null, self.property_hook ] end |
#case_item_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 4187 def case_item_parse parse_state = self.state if self.get_token(DEFAULT_REX) then self.get_token(COLON_REX) statement_or_null = self.statement_or_null_parse self.parse_error("statement or nothing expected") unless statement_or_null return self.case_item_hook(DEFAULT_TOK,statement_or_null) end cur_expression = self.expression_parse # self.parse_error("expression expected") unless cur_expression unless cur_expression then self.state = parse_state return nil end expressions = [ cur_expression ] loop do unless self.get_token(COMMA_REX) then break end cur_expression = self.expression_parse self.parse_error("expression expected") unless cur_expression expressions << cur_expression end unless self.get_token(COLON_REX) then # It was not an item self.state = parse_state return nil end statement_or_null = self.statement_or_null_parse self.parse_error("statement or nothing expected") unless statement_or_null return self.case_item_hook(expressions,statement_or_null) end |
#charge_strength_hook(type) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3187 def charge_strength_hook(type) return AST[:char_strength, type, self.property_hook ] end |
#charge_strength_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3171 def charge_strength_parse parse_state = self.state tok0 = self.get_token(OPEN_PAR_REX) tok1 = self.get_token(CHAR_STRENGH_REX) tok2 = self.get_token(CLOSE_PAR_REX) if !tok0 or !tok2 then self.state = parse_state return nil end unless tok1 self.state = parse_state return nil end return charget_strength_hook(tok1) end |
#combinational_entry_hook(level_input_list, output_symbol) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2135 def combinational_entry_hook(level_input_list, output_symbol) return AST[:combinational_entry, level_input_list,output_symbol, self.property_hook ] end |
#combinational_entry_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2120 def combinational_entry_parse parse_state = self.state level_input_list = self.level_input_list_parse if !level_input_list or !self.get_token(COLON_REX) then self.state = parse_state return nil end output_symbol = self._OUTPUT_SYMBOL_parse if !output_symbol or !self.get_token(SEMICOLON_REX) then self.state = parse_state return nil end return self.combinational_entry_hook(level_input_list,output_symbol) end |
#comment_hook(comment) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6916 def comment_hook(comment) return AST[:comment, comment, self.property_hook ] end |
#comment_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6904 def comment_parse short_comment = self.short_comment_parse if short_comment then return self.comment_hook(short_comment) end long_comment = self.long_comment_parse if long_comment then return self.comment_hook(long_comment) end return nil end |
#comment_text_hook(tok) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 7012 def comment_text_hook(tok) return AST[:comment_text, tok, self.property_hook ] end |
#comparison_term_hook(shift_terms) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6302 def comparison_term_hook(shift_terms) if self.state.compress and shift_terms.size == 1 then return shift_terms[0] else return AST[:comparison_term, shift_terms, self.property_hook ] end end |
#comparison_term_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6285 def comparison_term_parse # puts "comparison_parse" cur_shift_term = self.shift_term_parse return nil unless cur_shift_term shift_terms = [ cur_shift_term ] tok = nil loop do tok = self.get_token(SHIFT_OPERATOR_REX) break unless tok shift_terms << tok cur_shift_term = self.shift_term_parse self.parse_error("expression expected") unless cur_shift_term shift_terms << cur_shift_term end return comparison_term_hook(shift_terms) end |
#concatenation_hook(expressions) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6757 def concatenation_hook(expressions) return AST[:concatenation, expressions, self.property_hook ] end |
#concatenation_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6732 def concatenation_parse parse_state = self.state unless self.get_token(OPEN_CUR_REX) then self.state = parse_state return nil end cur_expression = self.expression_parse self.parse_error("expression expected") unless cur_expression expressions = [ cur_expression ] loop do unless self.get_token(COMMA_REX) then break end cur_expression = self.expression_parse self.parse_error("expression expected") unless cur_expression expressions << cur_expression end unless self.get_token(CLOSE_CUR_REX) then # Maybe it was a multiple concatenation, rewind and cancel. self.state = parse_state return nil end return self.concatenation_hook(expressions) end |
#condition_term_hook(logic_or_terms) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6072 def condition_term_hook(logic_or_terms) if self.state.compress and logic_or_terms.size == 1 then return logic_or_terms[0] else return AST[:condition_term, logic_or_terms, self.property_hook ] end end |
#condition_term_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6057 def condition_term_parse # puts "condition_term_parse" cur_logic_or_term = self.logic_or_term_parse return nil unless cur_logic_or_term logic_or_terms = [ cur_logic_or_term ] loop do break unless self.get_token(OR_OR_REX) logic_or_terms << OR_OR_TOK cur_logic_or_term = self.logic_or_term_parse self.parse_error("expression expected") unless cur_logic_or_term logic_or_terms << cur_logic_or_term end return condition_term_hook(logic_or_terms) end |
#conditional_port_expression_hook(port_reference__unary_operator, binary_operator, port_reference) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 5598 def conditional_port_expression_hook(port_reference__unary_operator, binary_operator, port_reference) return AST[:conditional_port_expression, port_reference__unary_operator, binary_operator, port_reference, self.property_hook ] end |
#conditional_port_expression_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 5574 def conditional_port_expression_parse unary_operator = self.unary_operator_parse port_reference0 = self.port_reference_parse if !port_reference0 then self.parse_error("there should be any of [#{UNARY_OPERATOR_TOKS.join(",")}] here") if unary_operator return nil end if unary_operator then return self.conditional_port_expression_hook(unary_operator, port_reference0,nil) end binary_operator = self.binary_operator_parse if binary_operator then port_reference1 = self.port_reference_parse self.parse_error("port reference expected here") unless port_reference1 return self.conditional_port_expression_hook(port_reference0, binary_operator, port_reference1) else return self.conditional_port_expression_hook(port_reference0, nil,nil) end end |
#constant_expression_hook(expression) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 5880 def constant_expression_hook(expression) return AST[:constant_expression, expression, self.property_hook ] end |
#constant_expression_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 5874 def constant_expression_parse expression = self.expression_parse return nil unless expression return self.constant_expression_hook(expression) end |
#continuous_assignment_hook(nettype, drive_strength, expandrange, delay, list_of_assignments) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2979 def continuous_assignment_hook(nettype, drive_strength, , delay, list_of_assignments) return AST[:continuous_assignment, nettype,drive_strength,,delay, list_of_assignments, self.property_hook ] end |
#continuous_assignment_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2956 def continuous_assignment_parse if self.get_token(ASSIGN_REX) then drive_strength = self.drive_strength_parse delay = self.delay_parse list_of_assignments = self.list_of_assignments_parse self.parse_error("semicolon expected HERE #5") unless self.get_token(SEMICOLON_REX) return continuous_assignment_hook(ASSIGN_TOK, drive_strength,nil, delay,list_of_assignments) else nettype = self._NETTYPE_parse return nil unless nettype drive_strength = self.drive_strength_parse = self. delay = self.delay_parse list_of_assignments = self.list_of_assignments_parse self.parse_error("semicolon expected HERE #6") unless self.get_token(SEMICOLON_REX) return continuous_assignment_hook(nettype, drive_strength,, delay,list_of_assignments) end end |
#controlled_timing_check_event_hook(timing_check_event_control, specify_terminal_descriptor, timing_check_condition) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 5259 def controlled_timing_check_event_hook( timing_check_event_control, specify_terminal_descriptor, timing_check_condition) return AST[:controlled_timing_check_event, timing_check_event_control, specify_terminal_descriptor, timing_check_condition, self.property_hook ] end |
#controlled_timing_check_event_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 5236 def controlled_timing_check_event_parse parse_state = self.state timing_check_event_control = self.timing_check_event_control_parse return nil unless timing_check_event_control specify_terminal_descriptor = self.specify_terminal_descriptor_parse unless specify_terminal_descriptor then self.state = parse_state return nil end unless self.get_token(AND_AND_AND_REX) then return self.controlled_timing_check_event_hook( timing_check_event_control, specify_terminal_descriptor, nil) end timing_check_condition = self.timing_check_condition_parse self.parse_error("timing check condition expected") unless timing_check_condition return self.controlled_timing_check_event_hook( timing_check_event_control, specify_terminal_descriptor, timing_check_condition) end |
#data_source_hook(expression) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 5725 def data_source_hook(expression) return AST[:data_source, expression, self.property_hook ] end |
#data_source_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 5717 def data_source_parse # *Auth*: the check are assumed to be done at the AST level. # If required, please redefine data_source_hook expression = self.expression_parse return nil unless expression return self.data_source_hook(expression) end |
#delay_control_hook(number__identifier__mintypmax_expression) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 7152 def delay_control_hook(number__identifier__mintypmax_expression) return AST[:delay_control, number__identifier__mintypmax_expression, self.property_hook ] end |
#delay_control_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 7133 def delay_control_parse unless self.get_token(SHARP_REX) then return nil end number = self.number_parse if number then return self.delay_control_hook(number) end identifier = self.identifier_parse if identifier then return self.delay_control_hook(identifier) end self.parse_error("opening parenthesis expected") unless self.get_token(OPEN_PAR_REX) mintypmax_expression = self.mintypmax_expression_parse self.parse_error("min:typical:max expression expected") unless mintypmax_expression self.parse_error("closing parenthesis expected") unless self.get_token(CLOSE_PAR_REX) return self.delay_control_hook(mintypmax_expression) end |
#delay_hook(number__identifier__mintypmax_expression, mintypmax_expression1, mintypmax_expression2) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3417 def delay_hook(mintypmax_expression__number, mintypmax_expression1, mintypexpression2) return AST[:delay, mintypmax_expression__number, mintypmax_expression1,mintypexpression2, self.property_hook ] end |
#delay_or_event_control_hook(base, arg0, arg1) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 4175 def delay_or_event_control_hook(base,arg0,arg1) return AST[:delay_or_event_control, base,arg0,arg1, self.property_hook ] end |
#delay_or_event_control_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 4153 def delay_or_event_control_parse if self.get_token(REPEAT_REX) then self.parse_error("opening parenthesis expected") unless self.get_token(OPEN_PAR_REX) expression = self.expression_parse self.parse_error("expression expected") unless expression self.parse_error("closing parenthesis expected") unless self.get_token(CLOSE_PAR_REX) event_control = self.event_control_parse self.parse_error("event control expected") unless event_control return self.delay_or_event_control_hook(REPEAT_TOK, expression,event_control) end delay_control = self.delay_control_parse if delay_control then return self.delay_or_event_control_hook(delay_control,nil,nil) end event_control = self.event_control_parse if event_control then return self.delay_or_event_control_hook(event_control,nil,nil) end return nil end |
#delay_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3375 def delay_parse unless self.get_token(SHARP_REX) then return nil end if self.get_token(OPEN_PAR_REX) then mintypmax_expression0 = self.mintypmax_expression_parse self.parse_error("min:typical:max delay expression expected") unless mintypmax_expression0 tok = self.get_token(COMMA_CLOSE_PAR_REX) if tok == COMMA_TOK then mintypmax_expression1 = self.mintypmax_expression_parse self.parse_error("min:typical:max delay expression expected") unless mintypmax_expression1 tok = self.get_token(COMMA_CLOSE_PAR_REX) if tok == COMMA_TOK then mintypmax_expression2 = self.mintypmax_expression_parse self.parse_error("min:typical:max delay expression expected") unless mintypmax_expression2 self.parse_error("closing parenthesis expected") unless self.get_token(CLOSE_PAR_REX) return self.delay_hook(mintypmax_expression0, mintypmax_expression1, mintypmax_expression2) elsif tok == CLOSE_PAR_TOK then return self.delay_hook(mintypmax_expression0, mintypmax_expression1,nil) else self.parse_error("comma or closing parenthesis expected") end elsif tok == CLOSE_PAR_TOK then return self.delay_hook(mintypmax_expression0,nil,nil) else self.parse_error("closing parenthesis expected") end end number = self.number_parse if number then return self.delay_hook(number,nil,nil) end identifier = self.identifier_parse if identifier then return self.delay_hook(identifier) end self.parse_error("identifier expected") end |
#description_hook(elem) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 1434 def description_hook(elem) if self.state.compress then return elem else return AST[:description, elem, self.property_hook ] end end |
#description_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 1422 def description_parse elem = self.module_parse if !elem then elem = self.udp_parse end if !elem then return nil if self.eof? self.parse_error("this is probably not a Verilog HDL file") end return self.description_hook(elem) end |
#drive_strength_hook(strengthL, strengthR) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3224 def drive_strength_hook(strengthL, strengthR) return AST[:drive_strength, strengthL,strengthR, self.property_hook ] end |
#drive_strength_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3198 def drive_strength_parse parse_state = self.state unless self.get_token(OPEN_PAR_REX) then return nil end strength0 = self._STRENGTH0_parse if !strength0 then strength1 = self._STRENGTH1_parse unless strength1 then self.state = parse_state return nil end self.parse_error("comma expected") unless self.get_token(COMMA_REX) strength0 = self._STRENGTH0_parse self.parse_error("one of [#{STRENGTH0_TOKS.join(",")}] expected") unless strength0 self.parse_error("closing parenthesis expected") unless self.get_token(CLOSE_PAR_REX) return drive_strength_hook(strength1, strength0) else self.parse_error("comma expected") unless self.get_token(COMMA_REX) strength1 = self._STRENGTH1_parse self.parse_error("one of [#{STRENGTH1_TOKS.join(",")}] expected") unless strength1 self.parse_error("closing parenthesis expected") unless self.get_token(CLOSE_PAR_REX) return drive_strength_hook(strength0, strength1) end end |
#each_origin_rule(&ruby_block) ⇒ Object
Access each origin rule.
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# File 'lib/HDLRuby/verilog_parser.rb', line 1375 def each_origin_rule(&ruby_block) # No ruby block? Return an enumerator. return to_enum(:each_origin_rule) unless ruby_block # A ruby block? Apply it on each rule value. orig = nil RULES.each do |k,v| orig = ORIGIN_RULES[k] orig ? ruby_block.(orig) : ruby_block.(v) end end |
#each_rule(&ruby_block) ⇒ Object
Access each rule.
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# File 'lib/HDLRuby/verilog_parser.rb', line 1367 def each_rule(&ruby_block) # No ruby block? Return an enumerator. return to_enum(:each_rule) unless ruby_block # A ruby block? Apply it on each rule value. RULES.each_value(&ruby_block) end |
#edge_control_specifier_hook(edge_descriptors) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 5317 def edge_control_specifier_hook(edge_descriptors) return AST[:edge_control_specifier, edge_descriptors, self.property_hook ] end |
#edge_control_specifier_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 5297 def edge_control_specifier_parse unless self.get_token(EDGE_REX) then return nil end self.parse_error("opening bracket expected") unless self.get_token(OPEN_BRA_REX) cur_edge_descriptor = self.edge_descriptor_parse self.parse_error("edge descriptor expected") unless cur_edge_descriptor edge_descriptors = [ cur_edge_descriptor ] loop do if self.get_token(COMMA_REX) then break end cur_edge_descriptor = self.edge_descriptor_parse self.parse_error("edge descriptor expected") unless cur_edge_descriptor edge_descriptors << cur_edge_descriptor end self.parse_error("closing bracket expected") unless self.get_token(CLOSE_BRA_REX) return self.edge_control_specifier_hook(edge_descriptors) end |
#edge_descriptor_hook(tok) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 5340 def edge_descriptor_hook(tok) return AST[:edge_descriptor, tok, self.property_hook ] end |
#edge_descriptor_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 5332 def edge_descriptor_parse tok = self.get_token(EDGE_DESCRIPTOR_REX) if tok then return self.edge_descriptor_hook(tok) end return nil end |
#edge_hook(edge) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2268 def edge_hook(edge) return AST[:edge, edge, self.property_hook ] end |
#edge_identifier_hook(tok) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 5745 def edge_identifier_hook(tok) return AST[:edge_identifier, tok, self.property_hook ] end |
#edge_identifier_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 5736 def edge_identifier_parse tok = self.get_token(EDGE_IDENTIFIER_REX) if tok then return self.edge_identifier_hook(tok) else return nil end end |
#edge_input_list_hook(level_symbols0, edge, level_symbols1) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2245 def edge_input_list_hook(level_symbols0, edge, level_symbols1) return AST[:edge_input_list, level_symbols0,edge,level_symbols1, self.property_hook ] end |
#edge_input_list_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2222 def edge_input_list_parse parse_state = self.state level_symbols0 = [] cur_level_symbol = nil loop do cur_level_symbol = self._LEVEL_SYMBOL_parse break unless cur_level_symbol level_symbols0 << cur_level_symbol end edge = self.edge_parse if !edge then self.state = parse_state return nil end level_symbols1 = [] loop do cur_level_symbol = self._LEVEL_SYMBOL_parse break unless cur_level_symbol level_symbols1 << cur_level_symbol end return self.edge_input_list_hook(level_symbols0,edge,level_symbols1) end |
#edge_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2256 def edge_parse if self.get_token(OPEN_PAR_REX) then level_symbol0 = self._LEVEL_SYMBOL_parse level_symbol1 = self._LEVEL_SYMBOL_parse self.parse_error("closing parenthesis expected") unless self.get_token(CLOSE_PAR_REX) edge = [ level_symbol0,level_symbol1 ] else edge = self._EDGE_SYMBOL_parse end return self.edge_hook(edge) end |
#edge_sensitive_path_declaration_hook(expression, edge_identifier, specify_input_terminal_descriptor, tok, specify_output_terminal_descriptor__list_of_path_outputs, polarity_operator, data_source_expression, path_delay_value) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 5698 def edge_sensitive_path_declaration_hook( expression, edge_identifier, specify_input_terminal_descriptor, tok, specify_output_terminal_descriptor__list_of_path_outputs, polarity_operator, data_source_expression, path_delay_value) return AST[:edge_sensitive_path_declaration, expression,edge_identifier, specify_input_terminal_descriptor,tok, spcify_output_terminal_descriptor__list_of_path_outputs, polarity_operator,data_source_expression,path_delay_value, self.property_hook ] end |
#edge_sensitive_path_declaration_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 5640 def edge_sensitive_path_declaration_parse parse_state = self.state unless self.get_token(IF_REX) then self.state = parse_state return nil end self.parse_error("opening parenthesis expected") unless self.get_token(OPEN_PAR_REX) expression = self.expression_parse edge_identifier = self.edge_identifier_parse specify_input_terminal_descriptor = self.specify_input_terminal_descriptor_parse if !specify_input_terminal_descriptor then self.state = parse_state return nil end if self.get_token(SEND_ARROW_REX) then self.parse_error("opening parenthesis expected") unless self.get_token(OPEN_PAR_REX) specify_output_terminal_descriptor = self.specify_output_terminal_Descriptor_parse self.parse_error("output terminal descriptor expected") unless specify_output_terminal_descriptor polarity_operator = self.polarity_operator_parse self.parse_error("colon expected") unless self.get_token(COLON_REX) data_source_expression = self.data_source_expression_parse self.parse_error("data source expression expected") unless data_source_expression self.parse_error("closing parenthesis expected") unless self.get_token(CLOSE_PAR_REX) self.parse_error("closing parenthesis expected") unless self.get_token(CLOSE_PAR_REX) self.parse_error("equal expected") unless self.get_token(EQUAL_REX) path_delay_value = self.path_delay_value_parse self.parse_error("path delay value expected") unless path_delay_value self.parse_error("semicolon expected") unless self.get_token(SEMICOLON_REX) return self.edge_sensitive_path_declaration_hook( expression,edge_identifier,specify_input_terminal_descriptor, tok,specify_output_terminal_descriptor,polarity_operator, data_source_expression,path_delay_value) elsif tok == ASTERISK_ARROW_TOK then self.parse_error("opening parenthesis expected") unless self.get_token(OPEN_PAR_REX) list_of_path_outputs = self.list_of_path_outputs_parse self.parse_error("list of path outputs expected") unless list_of_path_outputs polarity_operator = self.polarity_operator_parse self.parse_error("colon expected") unless self.get_token(COLON_REX) data_source_expression = self.data_source_expression_parse self.parse_error("data source expression expected") unless data_source_expression self.parse_error("closing parenthesis expected") unless self.get_token(CLOSE_PAR_REX) self.parse_error("closing parenthesis expected") unless self.get_token(CLOSE_PAR_REX) self.parse_error("equal expected") unless self.get_token(EQUAL_REX) path_delay_value = self.path_delay_value_parse self.parse_error("path delay value expected") unless path_delay_value self.parse_error("semicolon expected") unless self.get_token(SEMICOLON_REX) return self.edge_sensitive_path_declaration_hook( expression,edge_identifier,specify_input_terminal_descriptor, tok,list_of_path_outputs,polarity_operator, data_source_expression,path_delay_value) else self.state = parse_state return nil end end |
#eof? ⇒ Boolean
Tells if the end of file/string is reached (ignores the spaces and comments for this check)
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# File 'lib/HDLRuby/verilog_parser.rb', line 604 def eof? return (@state.text.match(/\G#{S}\z/,@state.index) != nil) end |
#equal_term_hook(comparison_terms) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6269 def equal_term_hook(comparison_terms) if self.state.compress and comparison_terms.size == 1 then return comparison_terms[0] else return AST[:equal_term, comparison_terms, self.property_hook ] end end |
#equal_term_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6252 def equal_term_parse # puts "equal_term_parse" cur_comparison_term = self.comparison_term_parse return nil unless cur_comparison_term comparison_terms = [ cur_comparison_term ] tok = nil loop do tok = self.get_token(COMPARISON_OPERATOR_REX) break unless tok comparison_terms << tok cur_comparison_term = self.comparison_term_parse self.parse_error("expression expected") unless cur_comparison_term comparison_terms << cur_comparison_term end return equal_term_hook(comparison_terms) end |
#event_control_hook(identifier__event_control) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 7178 def event_control_hook(identifier__event_control) return AST[:event_control, identifier__event_control, self.property_hook ] end |
#event_control_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 7163 def event_control_parse unless self.get_token(AT_REX) then return nil end identifier = self.identifier_parse if identifier then return self.event_control_hook(identifier) end self.parse_error("opening parenthesis expected") unless self.get_token(OPEN_PAR_REX) event_expression = self.event_expression_parse self.parse_error("event expression expected") unless event_expression self.parse_error("closing parenthesis expected") unless self.get_token(CLOSE_PAR_REX) return self.event_control_hook(event_expression) end |
#event_declaration_hook(name_of_events) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2945 def event_declaration_hook(name_of_events) return AST[:event_declaration, name_of_events, self.property_hook ] end |
#event_declaration_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2927 def event_declaration_parse # puts "event_declaration_parse" unless self.get_token(EVENT_REX) then return nil end cur_name_of_event = self.name_of_event_parse name_of_events = [ cur_name_of_event ] loop do unless self.get_token(COMMA_REX) then break end cur_name_of_event = self.name_of_event_parse name_of_events << cur_name_of_event end self.parse_error("semicolon expected") unless self.get_token(SEMICOLON_REX) return event_declaration_hook(name_of_events) end |
#event_expression_hook(event_primaries) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 7254 def event_expression_hook(event_primaries) return AST[:event_expression, event_primaries, self.property_hook ] end |
#event_expression_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 7241 def event_expression_parse cur_event_primary = self.event_primary_parse return nil unless cur_event_primary event_primaries = [ cur_event_primary ] loop do break unless self.get_token(EVENT_OR_COMMA_REX) cur_event_primary = self.event_primary_parse self.parse_error("event expression expected") unless cur_event_primary event_primaries << cur_event_primary end return event_expression_hook(event_primaries) end |
#event_primary_hook(tok__expression, event_expression) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 7284 def event_primary_hook(tok__expression, event_expression) return AST[:event_primary, tok__expression, event_expression, self.property_hook ] end |
#event_primary_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 7269 def event_primary_parse if self.get_token(MUL_REX) then return event_primary_hook(MUL_TOK,nil) end tok = self.get_token(EDGE_IDENTIFIER_REX) if tok then scalar_event_expression = self.scalar_event_expression_parse self.parse_error("scalar event expression expected") unless scalar_event_expression return self.event_primary_hook(tok,scalar_event_expression) end expression = self.expression_parse return nil unless expression return self.event_primary_hook(expression,nil) end |
#expandrange_hook(type, range) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2822 def (type, range) return AST[:expandrange, type,range, self.property_hook ] end |
#expandrange_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2806 def if self.get_token(SCALARED_REX) then range = self.range_parse self.parse_error("range expected") unless range return (SCALARED_TOK.to_sym, range) end if self.get_token(VECTORED_REX) then range = self.range_parse self.parse_error("range expected") unless range return (VECTORED_TOK.to_sym, range) end range = self.range_parse return nil unless range return (:"", range) end |
#expression_hook(string__condition_terms) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6040 def expression_hook(string__condition_terms) if self.state.compress and string__condition_terms.is_a?(Array) and string__condition_terms.size == 1 then return AST[:expression, string__condition_terms[0] ] else return AST[:expression, string__condition_terms, self.property_hook ] end end |
#expression_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6016 def expression_parse # puts "expression_parse" string = self._STRING_parse if string then return self.expression_hook(string) end cur_condition_term = self.condition_term_parse return nil unless cur_condition_term condition_terms = [ cur_condition_term ] loop do break unless self.get_token(QUESTION_REX) condition_terms << QUESTION_TOK cur_condition_term = self.condition_term_parse self.parse_error("expression expected") unless cur_condition_term condition_terms << cur_condition_term self.parse_error("colon expected") unless self.get_token(COLON_REX) condition_terms << COLON_TOK cur_condition_term = self.condition_term_parse self.parse_error("expression expected") unless cur_condition_term condition_terms << cur_condition_term end return expression_hook(condition_terms) end |
#file_error(error, lpos = @state.lpos) ⇒ Object
Generate a file error with origin indicated in +error+
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# File 'lib/HDLRuby/verilog_parser.rb', line 629 def file_error(error, lpos=@state.lpos) raise FileError.new(error,lpos) end |
#function_call_hook(name_of_function__name_of_system_function, expressions) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6851 def function_call_hook(name_of_function__name_of_system_function, expressions) return AST[:function_call, name_of_function__name_of_system_function, expressions, self.property_hook ] end |
#function_call_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6808 def function_call_parse parse_state = self.state name_of_function = self.name_of_function_parse if name_of_function then unless self.get_token(OPEN_PAR_REX) then self.state = parse_state return nil end cur_expression = self.expression_parse self.parse_error("expression expected") unless cur_expression expressions = [ cur_expression ] loop do unless self.get_token(COMMA_REX) then break end cur_expression = self.expression_parse self.parse_error("expression expected") unless cur_expression expressions << cur_expression end self.parse_error("closing parenthesis expected") unless self.get_token(CLOSE_PAR_REX) return self.function_call_hook(name_of_function,expressions) end name_of_system_function = self.name_of_system_function_parse return nil unless name_of_system_function if self.get_token(OPEN_PAR_REX) then cur_expression = self.expression_parse self.parse_error("expression expected") unless cur_expression expressions = [ cur_expression ] loop do unless self.get_token(COMMA_REX) then break end cur_expression = self.expression_parse self.parse_error("expression expected") unless cur_expression expressions << expression end self.parse_error("closing parenthesis expected") unless self.get_token(CLOSE_PAR_REX) return self.function_call_hook(name_of_system_function,expressions) else return self.function_call_hook(name_of_system_function,nil) end end |
#function_hook(range_or_type, name_of_function, tf_declarations, statement) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2436 def function_hook(range_or_type, name_of_function, tf_declarations, statement) return AST[:function, range_or_type,name_of_function,tf_declarations,statement, self.property_hook ] end |
#function_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2414 def function_parse unless self.get_token(FUNCTION_REX) then return nil else range_or_type = self.range_or_type_parse name_of_function = self.name_of_function_parse self.parse_error("name of function expected") unless self.get_token(SEMICOLON_REX) cur_tf_declaration = self.tf_declaration_parse self.parse_error("tf declaration expected") unless cur_tf_declaration tf_declarations = [ cur_tf_declaration ] loop do cur_tf_declaration = self.tf_declaration_parse break unless cur_tf_declaration tf_declarations << cur_tf_declaration end statement = self.statement_parse self.parse_error("'endfunction' expected") unless self.get_token(ENDFUNCTION_REX) return self.function_hook(range_or_type,name_of_function, tf_declarations,statement) end end |
#gate_declaration_hook(gatetype, drive_strength, delay, gate_instances) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3342 def gate_declaration_hook(gatetype, drive_strength, delay, gate_instances) return AST[:gate_declaration, gatetype,drive_strength,delay,gate_instances, self.property_hook ] end |
#gate_declaration_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3322 def gate_declaration_parse # puts "gate_declaration_parse" gatetype = self._GATETYPE_parse return nil unless gatetype drive_strength = self.drive_strength_parse delay = self.delay_parse cur_gate_instance = self.gate_instance_parse self.parse_error("gate instance expected") unless cur_gate_instance gate_instances = [ cur_gate_instance ] loop do break unless self.get_token(COMMA_REX) cur_gate_instance = self.gate_instance_parse self.parse_error("gate instance expected") unless cur_gate_instance gate_instances << cur_gate_instance end self.parse_error("semicolon expected") unless self.get_token(SEMICOLON_REX) return gate_declaration_hook(gatetype,drive_strength,delay, gate_instances) end |
#gate_instance_hook(name_of_gate_instance, terminals) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3451 def gate_instance_hook(name_of_gate_instance, terminals) return AST[:gate_instance, name_of_gate_instance,terminals, self.property_hook ] end |
#gate_instance_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3429 def gate_instance_parse parse_state = self.state name_of_gate_instance = self.name_of_gate_instance_parse unless self.get_token(OPEN_PAR_REX) then self.state = parse_state return nil end cur_terminal = self.terminal_parse unless cur_terminal then self.parse_error("terminal expected") end terminals = [ cur_terminal ] loop do break unless self.get_token(COMMA_REX) cur_terminal = self.terminal_parse self.parse_error("terminal expected") unless cur_terminal terminals << cur_terminal end self.parse_error("closing parenthesis expected") unless self.get_token(CLOSE_PAR_REX) return gate_instance_hook(name_of_gate_instance,terminals) end |
#get_token(rex) ⇒ Object
Get the token matching regexp +rex+ if any from current position. NOTE: it is assumed that rex starts with \G so that the maching really starts from current position of the parser and has a single capture for the token. Also assumes spaces are taken into account in the regexp.
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# File 'lib/HDLRuby/verilog_parser.rb', line 575 def get_token(rex) # puts "get_token at index=#{@state.index} and lpos=#{@state.lpos} with rex=#{rex} and char is #{@state.text[@state.index]}" # puts "text line is #{@state.text[(@[email protected])[email protected]]}" begin match = @state.text.match(rex,@state.index) rescue => error self.file_error(error) end if match then # There is a match, get the blanks and the token bls = match.captures[0] tok = match.captures[1] @state.index = match.end(0) @state.lpos += bls.scan(/\n/).size # spcs = bls.match(/[ \t]*\z/) # @state.cpos = spcs.end(0) - spcs.begin(0)+tok.length @state.cpos = 0 while @state.index > @state.cpos and !(@state.text[@state.index-@state.cpos] =~ /\n/) do @state.cpos += 1 end return tok else return nil end end |
#identifier_hook(identifiers) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 7036 def identifier_hook(identifiers) return AST[:identifier, *identifiers, self.property_hook ] end |
#identifier_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 7023 def identifier_parse cur_identifier = self._IDENTIFIER_parse return nil unless cur_identifier identifiers = [ cur_identifier ] loop do break unless self.get_token(DOT_REX) cur_identifier = self._IDENTIFIER_parse self.parse_error("identifier expected") unless cur_identifier identifiers << identifier end return self.identifier_hook(identifiers) end |
#init_val_hook(val) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2037 def init_val_hook(val) return AST[:init_val, val, self.property_hook ] end |
#init_val_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2031 def init_val_parse val = self.get_token(INIT_VAL_REX) self.parse_error("One of [#{INIT_VAL_TOKS.join(",")}] expected") unless val return self.init_val_hook(val) end |
#initial_statement_hook(statement) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3849 def initial_statement_hook(statement) return AST[:initial_statement, statement, self.property_hook ] end |
#initial_statement_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3840 def initial_statement_parse unless self.get_token(INITIAL_REX) then return nil end statement = self.statement_parse self.parse_error("statement expected") unless statement return self.initial_statement_hook(statement) end |
#inout_declaration_hook(type, sign, range, list_of_variables) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2684 def inout_declaration_hook(type, sign, range, list_of_variables) return AST[:inout_declaration, type,sign,range,list_of_variables, self.property_hook ] end |
#inout_declaration_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2671 def inout_declaration_parse # puts "inout_declaration_parse" unless self.get_token(INOUT_REX) then return nil end type = self.get_token(INOUTTYPE_REX) sign = self.get_token(SIGNED_REX) range = self.range_parse list_of_variables = self.list_of_variables_parse self.parse_error("semicolon expected") unless self.get_token(SEMICOLON_REX) return self.inout_declaration_hook(type,sign,range,list_of_variables) end |
#inout_port_declaration_hook(type, sign, range, name_of_variable) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 1753 def inout_port_declaration_hook(type, sign, range, name_of_variable) return AST[:inout_port_declaration, type,sign,range,name_of_variable, self.property_hook ] end |
#inout_port_declaration_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 1743 def inout_port_declaration_parse return nil unless self.get_token(INOUT_REX) type = self.get_token(INOUTTYPE_REX) sign = self.get_token(SIGNED_REX) range = self.range_parse name_of_variable = self.name_of_variable_parse self.parse_error("identifier expected") unless name_of_variable return inout_port_declaration_hook(type,sign,range,name_of_variable) end |
#input_declaration_hook(type, sign, range, list_of_variables) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2618 def input_declaration_hook(type, sign, range, list_of_variables) return AST[:input_declaration, type,sign,range,list_of_variables, self.property_hook ] end |
#input_declaration_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2604 def input_declaration_parse # puts "input_declaration_parse" unless self.get_token(INPUT_REX) then return nil end type = self.get_token(INPUTTYPE_REX) sign = self.get_token(SIGNED_REX) range = self.range_parse list_of_variables = self.list_of_variables_parse self.parse_error("identifier expected") unless list_of_variables self.parse_error("semicolon expected") unless self.get_token(SEMICOLON_REX) return self.input_declaration_hook(type,sign,range,list_of_variables) end |
#input_identifier_hook(identifier) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 4875 def input_identifier_hook(identifier) return AST[:input_identifier, identifier, self.property_hook ] end |
#input_identifier_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 4868 def input_identifier_parse # *Auth*: it should be checked that the identifier comes from # an input module. Left the the AST processing. identifier = self._IDENTIFIER_parse return self.input_identifier_hook(identifier) end |
#input_list_hook(input_list) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2186 def input_list_hook(input_list) if self.state.compress then return input_list else return AST[:input_list, input_list, self.property_hook ] end end |
#input_list_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2177 def input_list_parse input_list = self.edge_input_list_parse if !input_list then input_list = self.level_input_list_parse return nil unless input_list end return self.input_list_hook(input_list) end |
#input_port_declaration_hook(type, sign, range, name_of_variable) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 1710 def input_port_declaration_hook(type, sign, range, name_of_variable) return AST[:input_port_declaration, type,sign,range,name_of_variable, self.property_hook ] end |
#input_port_declaration_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 1700 def input_port_declaration_parse return nil unless self.get_token(INPUT_REX) type = self.get_token(INPUTTYPE_REX) sign = self.get_token(SIGNED_REX) range = self.range_parse name_of_variable = self.name_of_variable_parse self.parse_error("identifier expected") unless name_of_variable return input_port_declaration_hook(type,sign,range,name_of_variable) end |
#integer_declaration_hook(list_of_register_variables) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2897 def integer_declaration_hook(list_of_register_variables) return AST[:integer_declaration, list_of_register_variables, self.property_hook ] end |
#integer_declaration_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2887 def integer_declaration_parse # puts "integer_declaration_parse" unless self.get_token(INTEGER_REX) then return nil end list_of_register_variables = self.list_of_register_variables_parse self.parse_error("semicolon expected") unless self.get_token(SEMICOLON_REX) return integer_declaration_hook(list_of_register_variables) end |
#level_input_list_hook(level_symbols) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2212 def level_input_list_hook(level_symbols) return AST[:level_input_list, level_symbols, self.property_hook ] end |
#level_input_list_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2200 def level_input_list_parse cur_level_symbol = self._LEVEL_SYMBOL_parse return nil unless cur_level_symbol level_symbols = [ cur_level_symbol ] loop do cur_level_symbol = self._LEVEL_SYMBOL_parse break unless cur_level_symbol level_symbols << cur_level_symbol end return self.level_input_list_hook(level_symbols) end |
#level_sensitive_path_declaration_hook(conditional_port_expression, input, polarity_operator, tok, output, path_delay_value) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 5559 def level_sensitive_path_declaration_hook( conditional_port_expression, input, polarity_operator, tok, output, path_delay_value) return AST[:level_sensitive_path_declaration, input, polarity_operator, tok, output, path_delay_value, self.property_hook ] end |
#level_sensitive_path_declaration_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 5510 def level_sensitive_path_declaration_parse unless self.get_token(IF_REX) then return nil end self.parse_error("opening parenthesis expected") unless self.get_tokeen(OPEN_PAR_REX) conditional_port_expression = self.conditional_port_expression_parse self.parse_error("conditional port expression expected") unless conditional_port_expression self.parse_error("closing parenthesis expected") unless self.get_token(CLOSE_PAR_REX) self.parse_error("openning parenthesis expected") unless self.get_token(OPEN_PAR_REX) parse_state = self.state specify_input_terminal_descriptor = self.specify_input_terminal_descriptor_parse self.parse_error("input terminal descriptor expected") unless specify_input_terminal_descriptor polarity_operator = self.polarity_operator_parse if self.get_token(SEND_ARROW_REX) then # This is the right rule, go no specify_output_terminal_descriptor = self.specify_output_terminal_descriptor_parse self.parse_error("output terminal descriptor expected") unless specify_output_terminal_descriptor self.parse_error("closing parenthesis expected") unless self.get_token(CLOSE_PAR_REX) self.parse_error("equal expected") unless self.get_token(EQUAL_REX) path_delay_value = self.path_delay_value_parse self.parse_error("path delay value expected") unless path_delay_value self.parse_error("semicolon expected") unless self.get_token(SEMICOLON_REX) return self.level_sensitive_path_declaration_hook( conditional_port_expression, specify_input_terminal_descriptor, polarity_operator, tok, specify_output_terminal_descriptor, path_delay_value) else # This is maybe the other rule, rewind. self.state = parse_state list_of_path_inputs = self.list_of_path_inputs_parse self.parse_error("list of path inputs expected") unless list_of_path_inputs polarity_operator = self.polarity_operator_parse self.parse_error("'*>' expected") unless self.get_token(ASTERISK_ARROW_REX) list_of_path_outputs = self.list_of_path_outputs_parse self.parse_error("list of path outputs expected") unless list_of_path_outputs self.parse_error("closing parenthesis expected") unless self.get_token(CLOSE_PAR_REX) self.parse_error("equal expected") unless self.get_token(EQUAL_TOK_REX) path_delay_value = self.path_delay_value_parse self.parse_error("path delay value expected") unless path_delay_value self.parse_error("semicolon expected") unless self.get_token(SEMICOLON_REX) return self.level_sensitive_path_declaration_hook( conditional_port_expression, list_of_path_inputs, polarity_operator, tok, list_of_path_outputs, path_delay_value) end end |
#list_of_assignments_hook(assignments) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3309 def list_of_assignments_hook(assignments) return AST[:list_of_assigments, assignments, self.property_hook ] end |
#list_of_assignments_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3294 def list_of_assignments_parse cur_assignment = self.assignment_parse self.parse_error("assignment expected") unless cur_assignment assignments = [ cur_assignment ] loop do unless self.get_token(COMMA_REX) then break end cur_assignment = self.assignment_parse self.parse_error("assignment expected") unless cur_assignment assignments << cur_assignment end return list_of_assignments_hook(assignments) end |
#list_of_module_connections_hook(connections) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3772 def list_of_module_connections_hook(connections) return AST[:list_of_module_connections, connections, self.property_hook ] end |
#list_of_module_connections_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3743 def list_of_module_connections_parse cur_named_port_connection = self.named_port_connection_parse if cur_named_port_connection then named_port_connections = [ cur_named_port_connection ] loop do unless self.get_token(COMMA_REX) then break end cur_named_port_connection = self.named_port_connection_parse self.parse_error("named port connection expected") unless cur_named_port_connection named_port_connections << cur_named_port_connection end return list_of_module_connections_hook(named_port_connections) else cur_module_port_connection = self.module_port_connection_parse return nil unless cur_module_port_connection module_port_connections = [ cur_module_port_connection ] loop do unless self.get_token(COMMA_REX) then break end cur_module_port_connection = self.module_port_connection_parse self.parse_error("module port connection expected") unless cur_module_port_connection module_port_connections << cur_module_port_connection end return list_of_module_connections_hook(module_port_connections) end end |
#list_of_param_assignments_hook(param_assignments) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2568 def list_of_param_assignments_hook(param_assignments) return AST[:list_of_param_assignments, param_assignments, self.property_hook ] end |
#list_of_param_assignments_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2555 def list_of_param_assignments_parse cur_param_assignment = self.param_assignment_parse param_assignments = [ cur_param_assignment ] loop do unless self.get_token(COMMA_REX) then break end cur_param_assignment = self.param_assignment_parse param_assignments << cur_param_assignment end return self.list_of_param_assignments_hook(param_assignments) end |
#list_of_path_inputs_hook(specify_input_terminal_descriptors) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 4748 def list_of_path_inputs_hook(specify_input_terminal_descriptors) return AST[:list_of_path_inputs, specify_input_terminal_descriptors, self.property_hook ] end |
#list_of_path_inputs_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 4730 def list_of_path_inputs_parse cur_specify_input_terminal_descriptor = self.specify_input_terminal_descriptor_parse return nil unless cur_specify_input_terminal_descriptor specify_input_terminal_descriptors = [ cur_specify_input_terminal_descriptor ] loop do unless self.get_token(COMMA_REX) then break end cur_specify_input_terminal_descriptor = self.specify_input_terminal_descriptor_parse self.parse_error("input terminal descriptor expected") unless cur_specify_input_terminal_descriptor specify_input_terminal_descriptors << cur_specify_input_terminal_descriptor end return self.list_of_path_inputs_hook(specify_input_terminal_descriptors) end |
#list_of_path_outputs_hook(specify_output_terminal_descriptors) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 4777 def list_of_path_outputs_hook(specify_output_terminal_descriptors) return AST[:list_of_path_outputs, specify_output_terminal_descriptors, self.property_hook ] end |
#list_of_path_outputs_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 4759 def list_of_path_outputs_parse cur_specify_output_terminal_descriptor = self.specify_output_terminal_descriptor_parse return nil unless cur_specify_output_terminal_descriptor specify_output_terminal_descriptors = [ cur_specify_output_terminal_descriptor ] loop do unless self.get_token(COMMA_REX) then break end cur_specify_output_terminal_descriptor = self.specify_output_terminal_descriptor_parse self.parse_erro("output terminal descriptor expected") unless cur_specify_output_terminal_descriptor specify_output_terminal_descriptors << cur_specify_output_terminal_descriptor end return self.list_of_path_outputs_hook(specify_output_terminal_descriptors) end |
#list_of_ports_hook(ports) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 1574 def list_of_ports_hook(ports) return AST[:list_of_ports, ports, self.property_hook ] end |
#list_of_ports_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 1551 def list_of_ports_parse if self.get_token(OPEN_PAR_REX) then cur_port = self.port_parse ports = [ cur_port ] loop do if self.get_token(COMMA_REX) then cur_port = self.port_parse else if self.get_token(CLOSE_PAR_REX) then cur_port = nil else self.parse_error("comma of closing parenthesis expected") end end break unless cur_port ports << cur_port end return list_of_ports_hook(ports) else return nil end end |
#list_of_register_variables_hook(register_variables) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3063 def list_of_register_variables_hook(register_variables) return AST[:list_of_register_variables, register_variables, self.property_hook ] end |
#list_of_register_variables_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3050 def list_of_register_variables_parse cur_register_variable = self.register_variable_parse register_variables = [ cur_register_variable ] loop do unless self.get_token(COMMA_REX) break end cur_register_variable = self.register_variable_parse register_variables << cur_register_variable end return list_of_register_variables_hook(register_variables) end |
#list_of_variables_hook(name_of_variables) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3024 def list_of_variables_hook(name_of_variables) return AST[:list_of_variables, name_of_variables, self.property_hook ] end |
#list_of_variables_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3011 def list_of_variables_parse cur_name_of_variable = self.name_of_variable_parse name_of_variables = [ cur_name_of_variable ] loop do unless self.get_token(COMMA_REX) break end cur_name_of_variable = self.name_of_variable_parse name_of_variables << cur_name_of_variable end return list_of_variables_hook(name_of_variables) end |
#logic_and_term_hook(bit_or_terms) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6136 def logic_and_term_hook(bit_or_terms) if self.state.compress and bit_or_terms.size == 1 then return bit_or_terms[0] else return AST[:logic_and_term, bit_or_terms, self.property_hook ] end end |
#logic_and_term_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6119 def logic_and_term_parse # puts "logic_and_term_parse" cur_bit_or_term = self.bit_or_term_parse return nil unless cur_bit_or_term bit_or_terms = [ cur_bit_or_term ] tok = nil loop do tok = self.get_token(OR_OPERATOR_REX) break unless tok bit_or_terms << tok cur_bit_or_term = self.bit_or_term_parse self.parse_error("expression expected") unless cur_bit_or_term bit_or_terms << cur_bit_or_term end return logic_and_term_hook(bit_or_terms) end |
#logic_or_term_hook(logic_and_terms) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6103 def logic_or_term_hook(logic_and_terms) if self.state.compress and logic_and_terms.size == 1 then return logic_and_terms[0] else return AST[:logic_or_term, logic_and_terms, self.property_hook ] end end |
#logic_or_term_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6088 def logic_or_term_parse # puts "logic_or_term_parse" cur_logic_and_term = self.logic_and_term_parse return nil unless cur_logic_and_term logic_and_terms = [ cur_logic_and_term ] loop do break unless self.get_token(AND_AND_REX) logic_and_terms << AND_AND_TOK cur_logic_and_term = self.logic_and_term_parse self.parse_error("expression expected") unless cur_logic_and_term logic_and_terms << cur_logic_and_term end return logic_or_term_hook(logic_and_terms) end |
#long_comment_hook(comment_text) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6975 def long_comment_hook(comment_text) return AST[:long_comment, comment_text, self.property_hook ] end |
#long_comment_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6962 def long_comment_parse unless self.get_token(SLASH_ASTERISK_REX) then return nil end # comment_text = self.comment_text_parse # *Auth*: long and short comment are separated while in the # BNF the are the same rule. comment_text = self.long_comment_text_parse self.parse_error("comment text expected") unless comment_text self.parse_error("'*/' expected") unless self.get_token(ASTERISK_SLASH_REX) return self.long_comment_hook(comment_text) end |
#long_comment_text_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 7006 def long_comment_text_parse # *Auth*: long and short comment are separated while in the # BNF the are the same rule. return comment_text_hook(self.get_token(LONG_COMMENT_TEXT_REX)) end |
#lvalue_hook(identifier__concatenation, expression__constant_expression, constant_expression) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 5861 def lvalue_hook(identifier__concatenation, expression__constant_expression, constant_expression) return AST[:lvalue, identifier__concatenation, expression__constant_expression,constant_expression, self.property_hook ] end |
#lvalue_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 5833 def lvalue_parse concatenation = self.concatenation_parse if concatenation then return self.lvalue_hook(concatenation,nil,nil) end identifier = self.identifier_parse return nil unless identifier unless self.get_token(OPEN_BRA_REX) then return self.lvalue_hook(identifier,nil,nil) end parse_state = self.state constant_expression0 = self.constant_expression_parse if !constant_expression0 or !self.get_token(COLON_REX) then # Not constant_expression : constant_expression, rewind. self.state = parse_state expression = self.expression_parse self.parse_error("expression expected") unless expression self.parse_error("closing bracket expected") unless self.get_token(CLOSE_BRA_REX) return self.lvalue_hook(identifier,expression,nil) end self.parse_error("constant expression expected") unless constant_expression0 constant_expression1 = self.constant_expression_parse self.parse_error("constant expression expected") unless constant_expression1 self.parse_error("closing bracket expected") unless self.get_token(CLOSE_BRA_REX) return self.lvalue_hook(identifier, constant_expression0, constant_expression1) end |
#mintypmax_expression_hook(expression0, expression1, expression2) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 5906 def mintypmax_expression_hook(expression0, expression1, expression2) return AST[:mintypmax_expression, expression0,expression1,expression2, self.property_hook ] end |
#mintypmax_expression_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 5891 def mintypmax_expression_parse expression0 = self.expression_parse return nil unless expression0 unless self.get_token(COLON_REX) then return self.mintypmax_expression_hook(expression0,nil,nil) end expression1 = self.expression_parse self.parse_error("expression expected") unless expression1 self.parse_error("colon expected") unless self.get_token(COLON_REX) expression2 = self.expression_parse self.parse_error("expression expected") unless expression2 return self.mintypmax_expression_hook(expression0,expression1, expression2) end |
#module_hook(name, pre_parameter_declaration, ports, elems) ⇒ Object
,
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# File 'lib/HDLRuby/verilog_parser.rb', line 1501 def module_hook(name, pre_parameter_declaration, ports, elems) #, # timescale, celldefine) return AST[:module, name,pre_parameter_declaration,ports,elems, self.property_hook ]#, # timescale,celldefine] end |
#module_instance_hook(name_of_instance, list_of_module_connections) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3714 def module_instance_hook(name_of_instance, list_of_module_connections) return AST[:module_instance, name_of_instance,list_of_module_connections, self.property_hook ] end |
#module_instance_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3700 def module_instance_parse parse_state = self.state name_of_instance = self.name_of_instance_parse return nil unless name_of_instance unless self.get_token(OPEN_PAR_REX) then self.state = parse_state return nil end list_of_module_connections = self.list_of_module_connections_parse self.parse_error("closing parenthesis expected") unless self.get_token(CLOSE_PAR_REX) return module_instance_hook(name_of_instance, list_of_module_connections) end |
#module_instantiation_hook(name_of_module, parameter_value_assignment, module_instances) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3634 def module_instantiation_hook(name_of_module, parameter_value_assignment, module_instances) return AST[:module_instantiation, name_of_module,parameter_value_assignment, module_instances, self.property_hook ] end |
#module_instantiation_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3608 def module_instantiation_parse # puts "module_instantiation_parse" parse_state = self.state name_of_module = self.name_of_module_parse return nil unless name_of_module parameter_value_assignment = self.parameter_value_assignment_parse cur_module_instance = self.module_instance_parse unless cur_module_instance then self.state = parse_state return nil end module_instances = [ cur_module_instance ] loop do unless self.get_token(COMMA_REX) then break end cur_module_instance = self.module_instance_parse self.parse_error("module instance expected") unless cur_module_instance module_instances << cur_module_instance end self.parse_error("semicolon expected") unless self.get_token(SEMICOLON_REX) return module_instantiation_hook(name_of_module, parameter_value_assignment, module_instances) end |
#module_item_hook(item) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 1886 def module_item_hook(item) if self.state.compress then return item else return AST[:module_item, item, self.property_hook ] end end |
#module_item_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 1842 def module_item_parse item = self.parameter_declaration_parse return self.module_item_hook(item) if item item = self.input_declaration_parse return self.module_item_hook(item) if item item = self.output_declaration_parse return self.module_item_hook(item) if item item = self.inout_declaration_parse return self.module_item_hook(item) if item item = self.net_declaration_parse return self.module_item_hook(item) if item item = self.reg_declaration_parse return self.module_item_hook(item) if item item = self.time_declaration_parse return self.module_item_hook(item) if item item = self.integer_declaration_parse return self.module_item_hook(item) if item item = self.real_declaration_parse return self.module_item_hook(item) if item item = self.event_declaration_parse return self.module_item_hook(item) if item item = self.gate_declaration_parse return self.module_item_hook(item) if item item = self.module_instantiation_parse return self.module_item_hook(item) if item item = self.udp_instantiation_parse return self.module_item_hook(item) if item item = self.parameter_override_parse return self.module_item_hook(item) if item item = self.continuous_assignment_parse return self.module_item_hook(item) if item item = self.specify_block_parse return self.module_item_hook(item) if item item = self.initial_statement_parse return self.module_item_hook(item) if item item = self.always_statement_parse return self.module_item_hook(item) if item item = self.task_parse return self.module_item_hook(item) if item item = self.function_parse return self.module_item_hook(item) if item return nil end |
#module_name?(name) ⇒ Boolean
Tells if a name is a known module name.
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# File 'lib/HDLRuby/verilog_parser.rb', line 619 def module_name?(name) return @module_names.include?(name) end |
#module_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 1470 def module_parse if self.get_token(MODULE_MACROMODULE_REX) then # # Before parsing the module, get the timescale and celldefine # # properties from current position. # timescale = @state.lprop[@state.lpos][:timescale] # timescale = nil if timescale == "" # celldefine = @state.lprop[@state.lpos][:celldefine] # celldefine = nil if celldefine == "" # No parse name = self.name_of_module_parse pre_parameter_declaration = self.pre_parameter_declaration_parse ports = self.list_of_ports_parse self.parse_error("semicolon expected") unless self.get_token(SEMICOLON_REX) elems = [] cur_elem = nil loop do cur_elem = self.module_item_parse break unless cur_elem elems << cur_elem end self.parse_error("'endmodule' expected") unless self.get_token(ENDMODULE_REX) # Add a know module name. self.add_module_name(name) # And return the AST. return module_hook(name,pre_parameter_declaration,ports,elems) #, # timescale,celldefine) else return nil end end |
#module_port_connection_hook(expression) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3792 def module_port_connection_hook(expression) return AST[:module_port_connection, expression, self.property_hook ] end |
#module_port_connection_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3783 def module_port_connection_parse expression = self.expression_parse if expression then return module_port_connection_hook(expression) else return module_port_connection_hook(_NULL_hook) end end |
#mul_term_hook(unary_terms) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6400 def mul_term_hook(unary_terms) if self.state.compress and unary_terms.size == 1 then return unary_terms[0] else return AST[:mul_term, unary_terms, self.property_hook ] end end |
#mul_term_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6385 def mul_term_parse # puts "mul_term_parse" parse_state = self.state tok = self.get_token(UNARY_OPERATOR_REX) if tok then primary = self.primary_parse self.parse_error("expression expected") unless primary return mul_term_hook([tok,primary]) else primary = self.primary_parse return nil unless primary return mul_term_hook([primary]) end end |
#multiple_concatenation_hook(expression, expressions) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6796 def multiple_concatenation_hook(expression, expressions) return AST[:multiple_concatenation, expression,expressions, self.property_hook ] end |
#multiple_concatenation_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6767 def multiple_concatenation_parse parse_state = self.state unless self.get_token(OPEN_CUR_REX) then return nil end expression = self.expression_parse self.parse_error("expression expected") unless expression unless self.get_token(OPEN_CUR_REX) then # It is not a multiple concatenation, maybe it is a simple one. # Rewind and cancel. self.state = parse_state return nil end cur_expression = self.expression_parse self.parse_error("expression expected") unless cur_expression expressions = [ cur_expression ] loop do unless self.get_token(COMMA_REX) then break end cur_expression = self.expression_parse self.parse_error("expression expected") unless cur_expression expressions << expression end self.parse_error("closing curly bracket expected") unless self.get_token(CLOSE_CUR_REX) self.parse_error("closing curly bracket expected") unless self.get_token(CLOSE_CUR_REX) return self.multiple_concatenation_hook(expression,expressions) end |
#name_of_block_hook(identifier) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 4336 def name_of_block_hook(identifier) return AST[:name_of_block, identifier, self.property_hook ] end |
#name_of_block_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 4330 def name_of_block_parse identifier = self._IDENTIFIER_parse return nil unless identifier return self.name_of_block_hook(identifier) end |
#name_of_event_hook(identifier) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3159 def name_of_event_hook(identifier) return AST[:name_of_event, identifier, self.property_hook ] end |
#name_of_event_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3153 def name_of_event_parse identifier = self._IDENTIFIER_parse return nill unless identifier return name_of_event_hook(identifier) end |
#name_of_function_hook(identifier) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2481 def name_of_function_hook(name_of_function) return AST[:name_of_function, name_of_function, self.property_hook ] end |
#name_of_function_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2475 def name_of_function_parse identifier = self._IDENTIFIER_parse return nil unless identifier return self.name_of_function_hook(identifier) end |
#name_of_gate_instance_hook(identifier, range) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3468 def name_of_gate_instance_hook(identifier, range) return AST[:name_of_gate_instance, identifier,range, self.property_hook ] end |
#name_of_gate_instance_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3461 def name_of_gate_instance_parse identifier = self._IDENTIFIER_parse return nil unless identifier range = self.range_parse return name_of_gate_instance_hook(identifier,range) end |
#name_of_instance_hook(identifier, range) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3732 def name_of_instance_hook(identifier, range) return AST[:name_of_instance, identifier,range, self.property_hook ] end |
#name_of_instance_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3725 def name_of_instance_parse identifier = self._IDENTIFIER_parse return nil unless identifier range = self.range_parse return name_of_instance_hook(identifier,range) end |
#name_of_memory_hook(identifier) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3143 def name_of_memory_hook(identifier) return AST[:name_of_memory, identifier, self.property_hook ] end |
#name_of_memory_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3137 def name_of_memory_parse identifier = self._IDENTIFIER_parse return nil unless identifier return name_of_memory_hook(identifier) end |
#name_of_module_hook(identifier) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 1541 def name_of_module_hook(name) return AST[:name_of_module, name, self.property_hook ] end |
#name_of_module_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 1535 def name_of_module_parse name = self._IDENTIFIER_parse self.parse_error("module name identifier expected") if !name return self.name_of_module_hook(name) end |
#name_of_port_hook(name) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 1797 def name_of_port_hook(name) return AST[:name_of_port, name, self.property_hook ] end |
#name_of_port_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 1791 def name_of_port_parse name = self._IDENTIFIER_parse self.parse_error("port name identifier expected") if !name return self.name_of_port_hook(name) end |
#name_of_register_hook(identifier) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3127 def name_of_register_hook(identifier) return AST[:name_of_register, identifier, self.property_hook ] end |
#name_of_register_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3121 def name_of_register_parse identifier = self._IDENTIFIER_parse return nil unless identifier return name_of_register_hook(identifier) end |
#name_of_system_function_hook(identifier) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6890 def name_of_system_function_hook(identifier) return AST[:name_of_system_function, identifier, self.property_hook ] end |
#name_of_system_function_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6881 def name_of_system_function_parse # *Auth*: the $ is integrated into the system_identifier!! tok = self.get_token(SYSTEM_IDENTIFIER_REX) if tok then return self.name_of_system_function_hook(tok) end return nil end |
#name_of_system_task_hook(identifier) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 4497 def name_of_system_task_hook(identifier) return AST[:name_of_system_task, identifier, self.property_hook ] end |
#name_of_system_task_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 4490 def name_of_system_task_parse # *Auth*: the $ is integrated into the system_identifier!! identifier = self.system_identifier_parse return nil unless identifier return self.name_of_system_task_hook(identifier) end |
#name_of_task_hook(name_of_task) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2401 def name_of_task_hook(name_of_task) return AST[:name_of_task, name_of_task, self.property_hook ] end |
#name_of_task_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2395 def name_of_task_parse identifier = self._IDENTIFIER_parse return nil unless identifier return self.name_of_task_hook(identifier) end |
#name_of_udp_hook(identifier) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 1967 def name_of_udp_hook(name) return AST[:name_of_UDP, name, self.property_hook ] end |
#name_of_udp_instance_hook(identifier, range) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3573 def name_of_udp_instance_hook(identifier,range) return AST[:name_of_UDP_instance, identifier,range, self.property_hook ] end |
#name_of_udp_instance_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3566 def name_of_udp_instance_parse identifier = self.identifier_parse return nil unless identifier range = self.range_parse return name_of_udp_instance_hook(identifier,range) end |
#name_of_udp_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 1955 def name_of_udp_parse name = self._IDENTIFIER_parse # self.parse_error("name of UDP identifier expected") if !name return nil unless name if self.module_name?(identifier) then # This is a module name, not an UDP one. self.state = parse_state return nil end return name_of_udp_hook(name) end |
#name_of_variable_hook(identifier) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 1813 def name_of_variable_hook(name) return AST[:name_of_variable, name, self.property_hook ] end |
#name_of_variable_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 1807 def name_of_variable_parse name = self._IDENTIFIER_parse self.parse_error("variable name identifier expected") if !name return self.name_of_variable_hook(name) end |
#named_port_connection_hook(identifier, expression) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3827 def named_port_connection_hook(identifier, expression) return AST[:named_port_connection, identifier,expression, self.property_hook ] end |
#named_port_connection_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3814 def named_port_connection_parse unless self.get_token(DOT_REX) then return nil end identifier = self._IDENTIFIER_parse self.parse_error("identifier expected") unless identifier self.parse_error("opening parenthesis expected") unless self.get_token(OPEN_PAR_REX) expression = self.expression_parse self.parse_error("expression expected") unless expression self.parse_error("closing parenthesis expected") unless self.get_token(CLOSE_PAR_REX) return named_port_connection_hook(identifier,expression) end |
#net_declaration_hook(nettype_or_charge_strength, sign, expandrange, delay, list_of_variables_or_list_of_assignments) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2742 def net_declaration_hook(nettype_or_charge_strength, sign, , delay, list_of_variables_or_list_of_assignments) return AST[:net_declaration, nettype_or_charge_strength,sign,,delay, list_of_variables_or_list_of_assignments, self.property_hook ] end |
#net_declaration_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2705 def net_declaration_parse # puts "net_declaration_parse" nettype = self._NETTYPE_parse if nettype then drive_strength = self.drive_strength_parse if !drive_strength then sign = self.get_token(SIGNED_REX) = self. delay = self.delay_parse list_of_variables = self.list_of_variables_parse self.parse_error("semicolon expected HERE #1") unless self.get_token(SEMICOLON_REX) return net_declaration_hook(nettype,sign,,delay, list_of_variables) else sign = self.get_token(SIGNED_REX) = self. delay = self.delay_parse list_of_assignments = self.list_of_assignments_parse self.parse_error("semicolon expected HERE #2") unless self.get_token(SEMICOLON_REX) return net_declaration_hook(nettype,sign,,delay, list_of_assignments) end else unless self.get_token(TRIREG_REX) then return nil end charge_strength = self.charge_strength_parse sign = self.get_token(SIGNED_REX) = self. delay = self.delay_parse list_of_variables = self.list_of_variables_parse self.parse_error("semicolon expected HERE #3") unless self.get_token(SEMICOLON_REX) return net_declaration_hook(charge_strength,sign,,delay, list_of_variables) end end |
#next_state_hook(symbol) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2304 def next_state_hook(symbol) return AST[:next_state, symbol, self.property_hook ] end |
#next_state_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2295 def next_state_parse if self.get_token(HYPHEN_REX) then return next_state_hook(HYPHEN_TOK) else output_symbol = self._OUTPUT_SYMBOL_parse return self.next_state_hook(output_symbol) end end |
#non_blocking_assignment_hook(lvalue, delay_or_event_control, expression) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 4139 def non_blocking_assignment_hook(lvalue, delay_or_event_control, expression) return AST[:non_blocking_assignment, lvalue,delay_or_event_control,expression, self.property_hook ] end |
#non_blocking_assignment_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 4120 def non_blocking_assignment_parse parse_state = self.state lvalue = self.lvalue_parse return nil unless lvalue unless self.get_token(ASSIGN_ARROW_REX) then self.state = parse_state return nil end delay_or_event_control = self.delay_or_event_control_parse expression = self.expression_parse unless expression then self.state = parse_state return nil end return self.non_blocking_assignment_hook(lvalue, delay_or_event_control, expression) end |
#notify_register_hook(identifier) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 5493 def notify_register_hook(identifier) return AST[:notify_register, identifier, self.property_hook ] end |
#notify_register_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 5487 def notify_register_parse identifier = self.identifier_parse return nil unless identifier return self.notify_register_hook(identifier) end |
#number_hook(unsigned_number__decimal_number, base__unsigned_number, decimal_number) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6602 def number_hook(unsigned_number__decimal_number, base__unsigned_number, decimal_number) return AST[:number, unsigned_number__decimal_number, base__unsigned_number, decimal_number, self.property_hook ] end |
#number_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6575 def number_parse parse_state = self.state unsigned_number = self._UNSIGNED_NUMBER_parse base = self._BASE_parse if base then number = self._NUMBER_parse(base[0]) self.parse_error("number expected") unless number return self.number_hook(unsigned_number,base,number) end # Not a based number, rewind. self.state = parse_state decimal_number0 = self._DECIMAL_NUMBER_parse return nil unless decimal_number0 if self.get_token(DOT_REX) then unsigned_number = self._UNSIGNED_NUMBER_parse if self.get_token(E_REX) then decimal_number1 = self._DECIMAL_NUMBER_parse self.parse_error("decimal number expected") unless decimal_number1 return self.number_hook(decimal_number0,unsigned_number, decimal_number1) end self.parse_error("unsigned number expected") unless unsigned_number return self.number_hook(decimal_number0,unsigned_number,nil) end return self.number_hook(decimal_number0,nil,nil) end |
#origin_rule(name) ⇒ Object
Get an origin rule by +name+.
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# File 'lib/HDLRuby/verilog_parser.rb', line 1359 def origin_rule(name) name = name.to_sym res = ORIGIN_RULES[name] res = RULES[name] unless res return res end |
#output_declaration_hook(type, sign, range, list_of_variables) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2652 def output_declaration_hook(type, sign, range, list_of_variables) return AST[:output_declaration, type,sign,range,list_of_variables, self.property_hook ] end |
#output_declaration_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2637 def output_declaration_parse # puts "output_declaration_parse" unless self.get_token(OUTPUT_REX) then return nil end type = self.get_token(OUTPUTTYPE_REX) sign = self.get_token(SIGNED_REX) range = self.range_parse list_of_variables = self.list_of_register_variables_parse # list_of_variables = self.list_of_output_variables_parse # # Auth: semicolon included in list_of_output_variables! self.parse_error("semicolon expected") unless self.get_token(SEMICOLON_REX) return self.output_declaration_hook(type,sign,range,list_of_variables) end |
#output_identifier_hook(identifier) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 4892 def output_identifier_hook(identifier) return AST[:output_identifier, identifier, self.property_hook ] end |
#output_identifier_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 4885 def output_identifier_parse # *Auth*: it should be checked that the identifier comes from # an output module. Left the the AST processing. identifier = self.identifier_parse return self.output_identifier_hook(identifier) end |
#output_port_declaration_hook(type, sign, range, name_of_variable) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 1731 def output_port_declaration_hook(type, sign, range, name_of_variable) return AST[:output_port_declaration, type,sign,range,name_of_variable, self.property_hook ] end |
#output_port_declaration_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 1721 def output_port_declaration_parse return nil unless self.get_token(OUTPUT_REX) type = self.get_token(OUTPUTTYPE_REX) sign = self.get_token(SIGNED_REX) range = self.range_parse name_of_variable = self.name_of_variable_parse self.parse_error("identifier expected") unless name_of_variable return output_port_declaration_hook(type,sign,range,name_of_variable) end |
#output_terminal_name_hook(name_of_variable) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2053 def output_terminal_name_hook(name_of_variable) if self.state.compress then return name_of_variable else return AST[:output_terminal_name, name_of_variable, self.property_hook] end end |
#output_terminal_name_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2047 def output_terminal_name_parse name_of_variable = self.name_of_variable_parse return nil unless name_of_variable return self.output_terminal_name_hook(name_of_variable) end |
#par_block_hook(statements__name_of_block, block_declarations, statements) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 4318 def par_block_hook(statements__name_of_block, block_declarations, statements) return AST[:name_of_block, statements__name_of_block, block_declarations,statements, self.property_hook ] end |
#par_block_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 4281 def par_block_parse unless self.get_token(FORK_REX) then return nil end if self.get_token(COLON_REX) then name_of_block = self.name_of_block_parse self.parse_error("block name expected") unless name_of_block block_declarations = [ ] cur_block_declaration = nil loop do cur_block_declaration = self.block_declaration_parse break unless cur_block_declaration block_declarations << cur_block_declaration end statements = [] cur_statement = nil loop do cur_statement = self.statement_parse break unless cur_statement statements << cur_statement end self.parse_error("'join' expected") unless self.get_token(JOIN_REX) return self.par_block_hook(name_of_block,block_declarations, statements) else statements = [] cur_statement = nil loop do cur_statement = self.statement_parse break unless cur_statement statements << cur_statement end self.parse_error("'join' expected") unless self.get_token(JOIN_REX) return self.par_block_hook(statements,nil,nil) end end |
#param_assignment_hook(identifier, constant_expression) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2585 def param_assignment_hook(identifier, constant_expression) return AST[:param_assignment, identifier,constant_expression, self.property_hook ] end |
#param_assignment_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2578 def param_assignment_parse identifier = self.identifier_parse self.parse_error("equal expected") unless self.get_token(EQUAL_REX) constant_expression = self.constant_expression_parse return self.param_assignment_hook(identifier,constant_expression) end |
#parameter_declaration_hook(list_of_param_assignments) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2545 def parameter_declaration_hook(list_of_param_assignments) return AST[:parameter_declaration, list_of_param_assignments, self.property_hook ] end |
#parameter_declaration_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2535 def parameter_declaration_parse # puts "parameter_declaration_parse" unless self.get_token(PARAMETER_REX) then return nil end list_of_param_assignments = self.list_of_param_assignments_parse self.parse_error("semicolon expected") unless self.get_token(SEMICOLON_REX) return self.parameter_declaration_hook(list_of_param_assignments) end |
#parameter_override_hook(list_of_param_assignments) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3001 def parameter_override_hook(list_of_param_assignments) return AST[:parameter_override, list_of_param_assignments, self.property_hook ] end |
#parameter_override_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2992 def parameter_override_parse unless self.get_token(DEFPARAM_REX) then return nil end list_of_param_assignments = self.list_of_param_assignments_parse self.parse_error("semicolon expected") unless self.get_token(SEMICOLON_REX) return parameter_override_hook(list_of_param_assignments) end |
#parameter_value_assignment_hook(expressions) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3690 def parameter_value_assignment_hook(expressions) return AST[:parameter_value_assignment, expressions, self.property_hook ] end |
#parameter_value_assignment_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3670 def parameter_value_assignment_parse unless self.get_token(SHARP_REX) then return nil end self.parse_error("opening parenthesis expected") unless self.get_token(OPEN_PAR_REX) cur_expression = self.expression_parse self.parse_error("expression expected") unless cur_expression expressions = [ cur_expression ] loop do unless self.get_token(COMMA_REX) then break end cur_expression = self.expression_parse self.parse_error("expression expected") unless cur_expression expressions << cur_expression end self.parse_error("closing parenthesis expected") unless self.get_token(CLOSE_PAR_REX) return parameter_value_assignment_hook(expressions) end |
#parse ⇒ Object
Parse the Verilog HDL text. NOTE: does not support compiler directives, they must be preprocessed first using preprocess method.
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# File 'lib/HDLRuby/verilog_parser.rb', line 537 def parse # Initialize the state. @state.index = 0 @state.lpos = 1 @state.cpos = 1 # Initialize the list of known module names. @module_names = [] # Initialize the list of known UDP names. @udp_names = [] # Execute the parsing. return self.source_text_parse end |
#parse_error(msg, line_txt = nil, lpos = @state.lpos, cpos = @state.cpos, filename = ) ⇒ Object
Generate a parse error with message indicated by +msg+ and possible line text +line_text+, line number +lpos+, column +cpos+ and origin file name +filename+.
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# File 'lib/HDLRuby/verilog_parser.rb', line 636 def parse_error(msg, line_txt=nil, lpos=@state.lpos, cpos=@state.cpos, filename=@state.lprop[lpos][:filename]) # Maybe it was the main file. filename = @state.filename unless filename # Get the line where the error was. # First locate the position of the begining and the end of the line. # puts "lpos=#{lpos} line_txt=#{line_txt.class}" unless line_txt then blpos = @state.index-@state.cpos elpos = @state.index + @state.text.match(/[^\n]*/,@state.index).to_s.size # Address the case of invalid end of line (e.g., semicolon missing) if elpos == blpos then count = 1 while(@state.text[@state.index-count] =~ /[^\n]/) do count += 1 end cpos = count-1 blpos = elpos-count+1 end # The get the line. line_txt = @state.text[blpos...elpos] end # Raise an exception containing an error message made of msg, # the adjusted line number, its number, and the column where error # happended. raise ParseError.new(msg,line_txt,@state.lprop[lpos][:lpos],cpos, filename) end |
#path_declaration_hook(path_description, path_delay_value) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 4676 def path_declaration_hook(path_description, path_delay_value) return AST[:path_declaration, path_description,path_delay_value, self.property_hook ] end |
#path_declaration_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 4666 def path_declaration_parse path_description = self.path_description_parse return nil unless path_description self.parse_error("equal expected") unless self.get_token(EQUAL_REX) path_delay_value = self.path_delay_value_parse self.parse_error("path delay value expected") unless path_delay_value self.parse_error("semicolon expected") unless self.get_toekn == SEMICOLON_TOK return self.path_declaration_hook(path_description,path_delay_value) end |
#path_delay_expression_hook(mintypmax_expression) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 4984 def path_delay_expression_hook(mintypmax_expression) if self.state.compress then return mintypmax_expression else return AST[:path_delay_expression, mintypmax_expression, self.property_hook ] end end |
#path_delay_expression_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 4978 def path_delay_expression_parse mintypmax_expression = self.mintypmax_expression_parse return nil unless mintypmax_expression return path_delay_expression_hook(mintypmax_expression) end |
#path_delay_value_hook(path_delay_expression0, path_delay_expression1, path_delay_expression2, path_delay_expression3, path_delay_expression4, path_delay_expression5, path_delay_expression6, path_delay_expression7, path_delay_expression8, path_delay_expression9, path_delay_expression10, path_delay_expression11) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 4945 def path_delay_value_hook(path_delay_expression0, path_delay_expression1, path_delay_expression2, path_delay_expression3, path_delay_expression4, path_delay_expression5, path_delay_expression6, path_delay_expression7, path_delay_expression8, path_delay_expression9, path_delay_expression10, path_delay_expression11) return AST[:path_delay_value, path_delay_expression0, path_delay_expression1, path_delay_expression2, path_delay_expression3, path_delay_expression4, path_delay_expression5, path_delay_expression6, path_delay_expression7, path_delay_expression8, path_delay_expression9, path_delay_expression10, path_delay_expression11, self.property_hook ] end |
#path_delay_value_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 4914 def path_delay_value_parse parse_state = self.state if self.get_token(OPEN_PAR_REX) then cur_path_delay_expression = self.path_delay_expression_parse unless cur_path_delay_expression then self.state = parse_state return nil end path_delay_expressions = [ cur_path_delay_expression ] tok = nil 11.times do break unless self.get_token(COMMA_REX) cur_path_delay_expression = self.path_delay_expression_parse self.parse_error("path delay expression expected") unless cur_path_delay_expression path_delay_expressions << cur_path_delay_expression end self.parse_error("closing parenthesis expected") unless tok == CLOSE_PAR_TOK # Ensure there are 12 elements in the path_delay_expressions if path_delay_expressions.size < 12 then path_delay_expressions[11] = nil end return self.path_delay_value_hook(*path_delay_expressions) else path_delay_expression = self.path_delay_expression_parse return nil unless path_delay_expression return self.path_delay_value_hook(path_delay_expression, nil,nil,nil,nil,nil,nil, nil,nil,nil,nil,nil) end end |
#path_description_hook(type, input, output) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 4720 def path_description_hook(type, input, output) return AST[:path_description, type,input,output, self.property_hook ] end |
#path_description_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 4687 def path_description_parse parse_state = self.state unless self.get_token(OPEN_PAR_REX) then self.state = parse_state return nil end specify_input_terminal_descriptor = self.specify_input_terminal_descriptor_parse if self.get_token(SEND_ARROW_REX) and specify_input_terminal_descriptor then specify_output_terminal_descriptor = self.specify_output_terminal_descriptor_parse self.parse_error("output terminal descriptor expected") unless specify_output_terminal_descriptor self.parse_error("closing parenthesis expected") unless self.get_token(CLOSE_PAR_REX) return self.path_description_hook(SEND_ARROW_TOK, specify_input_terminal_descriptor, specify_output_terminal_descriptor) end list_of_path_inputs = self.list_of_path_inputs_parse unless list_of_path_inputs then self.state = parse_state return nil end unless self.get_token(ASTERISK_ARROW_REX) then self.state = parse_state end list_of_path_outputs = self.list_of_path_outputs_parse self.parse_error("list of path outputs expected") unless list_of_path_outputs return self.path_description_hook(ASTERIS_ARROW_TOK, list_of_path_inputs, list_of_path_outputs) end |
#peek_token(rex) ⇒ Object
Check the token matching regexp +rex+ from current position. Returns the match in case of success and nil otherwise but do not change the state of the parser.
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# File 'lib/HDLRuby/verilog_parser.rb', line 566 def peek_token(rex) return @state.text.match(rex,@state.index) end |
#polarity_operator_hook(tok) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 5623 def polarity_operator_hook(tok) return AST[:polarity_operator, tok, self.property_hook ] end |
#polarity_operator_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 5614 def polarity_operator_parse tok = self.get_token(POLARITY_OPERATOR_REX) if tok then return polarity_operator_hook(tok) else return nil end end |
#port_expression_hook(port_declaration__port_refs) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 1688 def port_expression_hook(port_declaration__port_refs) return AST[:port_expression, port_declaration__port_refs, self.property_hook ] end |
#port_expression_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 1642 def port_expression_parse input_port_declaration = self.input_port_declaration_parse if input_port_declaration then return port_expression_hook(input_port_declaration) end output_port_declaration = self.output_port_declaration_parse if output_port_declaration then return port_expression_hook(output_port_declaration) end inout_port_declaration = self.inout_port_declaration_parse if inout_port_declaration then return port_expression_hook(inout_port_declaration) end parse_state = self.state port_refs = [ ] cur_port_ref = self.port_reference_parse if cur_port_ref then port_refs << cur_port_ref else unless self.get_token(OPEN_CUR_REX) then self.state = parse_state return nil end port_refs << cur_port_ref cur_port_ref = self.port_reference_parse if !cur_port_ref then self.state = parse_state return nil end loop do if self.get_token(COMMMA_REX) then cur_port_ref = self.port_reference_parse end if self.get_token(CLOSE_CUR_REX) then cur_port_ref = nil else self.parse_error("comma or closing parenthesis expected") end break unless cur_port_ref port_refs << cur_port_ref end end return self.port_expression_hook(port_refs) end |
#port_hook(port_expression__name_of_port, port_expression) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 1602 def port_hook(port_expression__name_of_port, port_expression) return AST[:port, port_expression__name_of_port,port_expression, self.property_hook ] end |
#port_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 1585 def port_parse port_expression = self.port_expression_parse if port_expression then return self.port_hook(port_expression,nil) end unless self.get_token(DOT_REX) then return nil end name_of_port = self.name_of_port_parse self.parse_error("name of port expected") unless name_of_port self.parse_error("opening parenthesis expected") unless self.get_token(OPEN_PAR_REX) port_expression = self.port_expression_parse self.parse_error("port expression expected") unless port_expression self.parse_error("closing parenthesis expected") unless self.get_token(CLOSE_PAR_REX) return self.port_hook(name_of_port,port_expression) end |
#port_reference_hook(name, const0, const1) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 1781 def port_reference_hook(name,const0,const1) return AST[:port_reference, name,const0,const1, self.property_hook ] end |
#port_reference_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 1766 def port_reference_parse name = self.name_of_variable_parse const0, const1 = nil, nil if self.get_token(OPEN_BRA_REX) then const0 = self.constant_expression_parse self.parse_error("constant expression expected") unless const0 if self.get_token(COLON_REX) then const1 = self.constant_expression_parse self.parse_error("constant expression expected") unless const1 end self.parse_error("closing bracket expected") unless self.get_token(CLOSE_BRA_REX) end return self.port_reference_hook(name,const0,const1) end |
#pre_parameter_declaration_hook(list_of_param_assignments) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 1524 def pre_parameter_declaration_hook(list_of_param_assignments) return AST[:pre_parameter_declaration, list_of_param_assignments, self.property_hook ] end |
#pre_parameter_declaration_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 1514 def pre_parameter_declaration_parse return nil unless self.get_token(SHARP_REX) self.parse_error("opening parenthesis expected") unless self.get_token(OPEN_PAR_REX) self.parse_error("parameter expected") unless self.get_token(PARAMETER_REX) list_of_param_assignments = self.list_of_param_assignments_parse self.parse_error("parameter assignment expected") unless list_of_param_assignments self.parse_error("closing parenthesis expected") unless self.get_token(CLOSE_PAR_REX) return pre_parameter_declaration_hook(list_of_param_assignments) end |
#preprocess ⇒ Object
Preprocess the Verilog HDL text with directives.
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# File 'lib/HDLRuby/verilog_parser.rb', line 213 def preprocess # Initialize the preprocessing variables. macro_cons = {} # The set of macro constants. macro_func = {} # The set of macro functions. lpos = 1 # Current line number in text. cur_timescale = "" # The Current time scale # The initial text becomes the text to preprocesses whereas # the text to parse is cleared. pre_text = @state.text @state.text = "" # Initialize the line jump (1 if no line merge). ljump = 1 # Initialize the lines properties. # @state.lprop = [ { lpos: 0, timescale: "", celldefine: "" }] @state.lprop = [ { lpos: 0 }] # Initialize the line skip mode for handling the `ifdef and `ifndef # directives. skip_mode = [ [:start, false] ] # Preprocessing is grammatically straight foward, so use # a StringScanner. scanner = StringScanner.new(pre_text) while(!scanner.eos?) do # Set the default propery of the line if none. if !@state.lprop[lpos] then @state.lprop[lpos] = @state.lprop[lpos-1].clone # But not the freeze state. @state.lprop[lpos].delete(:lfreeze) @state.lprop[lpos][:lpos] = @state.lprop[lpos-1][:lpos] + 1 else # Still need to update the timescale and celldefine properties. @state.lprop[lpos][:timescale] = @state.lprop[lpos-1][:timescale] @state.lprop[lpos][:celldefine] = @state.lprop[lpos-1][:celldefine] end # Set the default filename if none. unless @state.lprop[lpos][:filename] then @state.lprop[lpos][:filename] = @state.filename end # puts "lpos=#{lpos} @state.lprop[lpos]=#{@state.lprop[lpos]}" # Is it a directive line? begin line = scanner.scan(/[ \t]*`[^\n]*\n/) rescue => error # Problem in the text, so fix it first. estr = scanner.string.scrub("\uFFFD") # And locate the error. elpos = 1 ecpos = nil eline = nil estr.lines do |line| elpos = elpos + 1 unless @state.lprop[elpos] then if elpos > 1 then @state.lprop[elpos] = @state.lprop[elpos-1] else @state.lprop[elpos] = { :lpos => 1, :filename => @state.filename } end @state.lprop[elpos][:lpos] += 1 end eline = line ecpos = line.index("\uFFFD") break if ecpos end if ecpos then # It was an invalid, non-UTF8, character. self.parse_error("non UTF-8 character", eline.chomp,elpos,ecpos) else # It was another kind of error. self.file_error(error,@state.lprop[lpos][:lpos]) end end if line then # Yes, process it. # But, first, are there any line merge? line,jump = self.process_merge_line(line,scanner,lpos) # Get the kind of macro and its arguments. type,code = line.scan(/^\s*`[a-zA-Z]+|[^`]*$/) type.gsub!(/\s/,"") # Add the skip mode: X at the end if skipped. type += "X" if skip_mode[-1][1] # Depending of the kind of macro. case type when "`timescaleX" # Skip when "`timescale" # Process and check to code. code = code.gsub(/\s/,"") mcode = code.match(/^([0-9]+)(s|ms|us|ns|ps|fs)\/([0-9]+)(s|ms|us|ns|ps|fs)/) # Compute the position of the code, used in case of error. cpos = line.scan(/\s*`timescale\s*/)[0].size unless mcode then self.parse_error("invalid timescale format", line.chomp,lpos,cpos) end unit = mcode.captures[0].to_i * FS_TIME[mcode.captures[1]] prec = mcode.captures[2].to_i * FS_TIME[mcode.captures[3]] unless unit > prec then self.parse_error( "in timescale, unit shoud be greater than precision", line.chomp,lpos,cpos) end # puts "unit=#{unit} precision=#{prec}" # @state.lprop[lpos][:timescale] = AST[:timescale, unit, prec ] @state.lprop[lpos][:timescale] = [ unit, prec ] when "`celldefineX" # Skip when "`celldefine" # @state.lprop[lpos][:celldefine] = AST[:celldefine] @state.lprop[lpos][:celldefine] = true when "`endcelldefineX" # Skip when "`endcelldefine" @state.lprop[lpos][:celldefine] = false when "`defineX" # Skip when "`define" # Get the macro name, arguments and replacement. name,args,replace = code.scan(/^\s*[_a-zA-Z][_a-zA-Z0-9]*|\(.*\)|.*$/) # Process the name. unless name =~ /^\s*[_a-zA-Z][_a-zA-Z0-9]*/ then cpos = line.scan(/\s*`define\s*/)[0].size self.parse_error("invalid macro name",line.chomp,lpos,cpos) end name.gsub!(/\s/,"") # Process the arguments if any. if args[0] == "(" then # There are indeed arguments, it is a macro function. args = args.split(/[\(\),]/).reject { |arg| arg.empty? } # Process the arguments. cpos = line.index("(") args.map! do |arg| cpos += 1 unless arg =~ /^\s*[_a-zA-Z][_a-zA-Z0-9]*\s*$/ then self.parse_error("invalid macro argument", line.chomp,lpos,cpos) end cpos += arg.size /#{arg.gsub(/\s/,"")}(?=[^_a-zA-Z0-9])/ end # Add the macro function. macro_func[name] = [ /`#{name}\([^\(]*\)/, args, replace ] # Remove the macro constant if any to avoid conflict. macro_cons.delete(name) else # There are no arguments, it is a macro constant. macro_cons[name] = [ /`#{name}(?=[^_a-zA-Z0-9])/, args ] # Remove the macro function if any to avoid conflict. macro_func.delete(name) end when "`undefX" # Skip when "`undef" # Get the macro name, arguments and replacement. name = code.scan(/^\s*[_a-zA-Z][_a-zA-Z0-9]*\s*$/)[0] # Process the name. name.gsub!(/\s/,"") # Remove the macro. macro_cons.delete(name) macro_func.delete(name) when "`ifdefX" # Skip when "`ifdef" # Get the macro name, arguments and replacement. name = code.scan(/^\s*[_a-zA-Z][_a-zA-Z0-9]*\s*$/)[0] unless name =~ /^\s*[_a-zA-Z][_a-zA-Z0-9]*/ then cpos = line.scan(/\s*`ifdef\s*/)[0].size self.parse_error("invalid macro name",line.chomp,lpos,cpos) end # Process the name. name.gsub!(/\s/,"") # Set the the skip mode on if there is no such macro. if macro_cons.key?(name) or macro_func.key?(name) skip_mode << [ :ifdef, false ] else skip_mode << [ :ifdef, true ] end when "`ifndefX" # Skip when "`ifndef" # Get the macro name, arguments and replacement. name = code.scan(/^\s*[_a-zA-Z][_a-zA-Z0-9]*\s*$/)[0] unless name =~ /^\s*[_a-zA-Z][_a-zA-Z0-9]*/ then cpos = line.scan(/\s*`ifndef\s*/)[0].size self.parse_error("invalid macro name",line.chomp,lpos,cpos) end # Process the name. name.gsub!(/\s/,"") # Set the the skip mode on if there is such macro. if macro_cons.key?(name) or macro_func.key?(name) skip_mode << [ :ifndef, true ] else skip_mode << [ :ifndef, false ] end when "`else", "`elseX" # Invert the last skip mode if any, otherwise, error. if skip_mode.size < 2 then self.parse_error("misplaced `else directive", line.chomp,lpos,0) end skip_mode[-1] = [:else, !skip_mode[-1][1] ] when "`elsif", "`elsifX" # Get the macro name, arguments and replacement. name = code.scan(/^\s*[_a-zA-Z][_a-zA-Z0-9]*\s*$/)[0] unless name =~ /^\s*[_a-zA-Z][_a-zA-Z0-9]*/ then cpos = line.scan(/\s*`elsifX?\s*/)[0].size self.parse_error("invalid macro name",line.chomp,lpos,cpos) end # Process the name. name.gsub!(/\s/,"") # Depending of the skip mode. if (skip_mode[-1][0]==:ifdef or skip_mode[-1][0]==:ifndef) and skip_mode[-1][1] then # Set the the skip mode on if there is such macro. if macro_cons.key?(name) or macro_func.key?(name) # This is an elsif so replace the last skip mode. skip_mode[-1] = [ :ifdef, false ] else # This is an elsif so replace the last skip mode. skip_mode[-1] [ :ifdef, true ] end else self.parse_error("misplaced `elsif directive", line.chomp,lpos,0) end when "`endif", "`endifX" # Remove the last skip mode if any, otherwise, error. if skip_mode.size < 2 then self.parse_error("misplaced `endif directive", line.chomp,lpos,0) end skip_mode.pop when "`includeX" when "`include" # Get the file name to include. filename = code.scan(/^\s*"[^\\"]*"\s*$/)[0] filename.gsub!(/^\s*/,"") filename.gsub!(/"\s*$/,"\"") filename = filename[1..-2] # Reads the file. included_text = "" begin included_text = File.read(@state.path + filename) rescue => error self.file_error(error,lpos+ljump) end # Insert it in pre_text and not in final text so that it # is processed again, and setup again the scanner. new_pos = scanner.pos-line.size+1 pre_text = pre_text[0...new_pos] + included_text + pre_text[scanner.pos..-1] scanner = StringScanner.new(pre_text) scanner.pos = new_pos # Also update the line numbering and file reference. included_jump = included_text.lines.count # puts "included_jump=#{included_jump} ljump=#{ljump}" idx = 0 included_jump.times do |i| idx = lpos+i+ljump-1 @state.lprop[idx] = @state.lprop[idx-1].clone # i-1 to compenstate the later line increase. @state.lprop[idx][:lpos] = i-1 @state.lprop[idx][:filename] = @state.path + filename end # puts "lpos=#{lpos} @state.lprop[lpos]=#{@state.lprop[lpos]}" next_lpos = lpos+included_jump @state.lprop[next_lpos] = @state.lprop[lpos-1].clone @state.lprop[next_lpos][:lpos] += ljump @state.lprop[next_lpos][:lfreeze] = true when "`resetallX" # Skip when "`resetall" # Clears the macro. # Auth: that what it should do right? macro_cons.clear macro_func.clear else cpos = line.index("`") self.parse_error("unknown directive",line.chomp,lpos,cpos) end # And add an empty line instead to the final text. @state.text << "\n" else # No, get it as a normal line. line = scanner.scan(/[^\n]*\n/) # But, first, are there any line merge? line,ljump = self.process_merge_line(line,scanner,lpos) # Shall we skip? if skip_mode[-1][1] then # Yes, the line is empty. line = "\n" else # Also, this time, there will be some line position adjustment. # And apply the known macros. macro_cons.each_value do |rex,replace| line.gsub!(rex,replace) end macro_func.each_value do |rex,formal_args,replace| # Extract all the macro function call macro_calls = line.scan(rex) # Process them to replacements. macro_calls.each do |mc| real_args = mc.split(/[\(\),]/)[1..-1] # puts "real_args=#{real_args} formal_args=#{formal_args}" formal_args.each_with_index do |formal_arg,i| replace = replace.gsub(formal_arg,real_args[i]) end line.sub!(mc,replace) end end end # Write the line to the final text. @state.text << line end # Next line. lpos += ljump end # Are all the `ifdef and `ifndef directive closed? if skip_mode.size > 1 then # No, error. self.parse_error("`endif directive missing",line.chomp,lpos,0) end # puts "Result: #{@state.text}" # puts "lprops=#{@state.lprop.join("\n")}" end |
#primary_hook(base, expression__constant_expression, constant_expression) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6537 def primary_hook(base, expression__constant_expression, constant_expression) return AST[:primary, base, expression__constant_expression, constant_expression, self.property_hook ] end |
#primary_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6490 def primary_parse number = self.number_parse if number then return self.primary_hook(number,nil,nil) end multiple_concatenation = self.multiple_concatenation_parse if multiple_concatenation then return self.primary_hook(multiple_concatenation,nil,nil) end concatenation = self.concatenation_parse if concatenation then return self.primary_hook(concatenation,nil,nil) end function_call = self.function_call_parse if function_call then return self.primary_hook(function_call,nil,nil) end if self.get_token(OPEN_PAR_REX) then mintypmax_expression = self.mintypmax_expression_parse if !mintypmax_expression then return nil end self.parse_error("closing parenthesis expected") unless self.get_token(CLOSE_PAR_REX) return self.primary_hook(mintypmax_expression,nil,nil) end identifier = self.identifier_parse return nil unless identifier unless self.get_token(OPEN_BRA_REX) then return self.primary_hook(identifier,nil,nil) end parse_state = self.state constant_expression0 = self.constant_expression_parse if !constant_expression0 or !self.get_token(COLON_REX) then # Not constant_expression : constant_expression, rewind self.state = parse_state expression = self.expression_parse self.parse_error("expression expected") unless expression self.parse_error("closing bracket expected") unless self.get_token(CLOSE_BRA_REX) return self.primary_hook(identifier,expression,nil) end constant_expression1 = self.constant_expression_parse self.parse_error("constant expression expected") unless constant_expression1 self.parse_error("closing bracket expected") unless self.get_token(CLOSE_BRA_REX) return self.primary_hook(identifier, constant_expression0,constant_expression1) end |
#property_hook ⇒ Object
Hook for the properties of the current line. (No syntax rule required).
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# File 'lib/HDLRuby/verilog_parser.rb', line 1389 def property_hook return AST[:property, @state.lprop[@state.lpos].select {|k,v| v} ] end |
#range_hook(constant_expression0, constant_expression1) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3284 def range_hook(constant_expression0, constant_expression1) return AST[:range, constant_expression0,constant_expression1, self.property_hook ] end |
#range_or_type_hook(range_or_type) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2461 def range_or_type_hook(range_or_type) if self.state.compress then return range_or_type else return AST[:range_or_type, range_or_type, self.property_hook ] end end |
#range_or_type_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2450 def range_or_type_parse tok = self.get_token(INTEGER_REAL_REX) if tok then return self.range_or_type_hook(tok) else range = self.range_parse return nil unless range return self.range_or_type_hook(range) end end |
#range_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3270 def range_parse parse_state = self.state return nil unless self.get_token(OPEN_BRA_REX) constant_expression0 = self.constant_expression_parse if !constant_expression0 or !self.get_token(COLON_REX) then self.state = parse_state return nil end constant_expression1 = self.constant_expression_parse self.parse_error("constant expression expected") unless constant_expression1 self.parse_error unless self.get_token(CLOSE_BRA_REX) return range_hook(constant_expression0,constant_expression1) end |
#real_declaration_hook(list_of_register_variables) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2917 def real_declaration_hook(list_of_register_variables) return AST[:real_declaration, list_of_register_variables, self.property_hook ] end |
#real_declaration_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2907 def real_declaration_parse # puts "real_declaration_parse" unless self.get_token(REAL_REX) then return nil end list_of_register_variables = self.list_of_register_variables_parse self.parse_error("semicolon expected") unless self.get_token(SEMICOLON_REX) return real_declaration_hook(list_of_register_variables) end |
#reg_declaration_hook(sign, range, list_of_register_variables) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2852 def reg_declaration_hook(sign, range, list_of_register_variables) return AST[:reg_declaration, sign,range,list_of_register_variables, self.property_hook ] end |
#reg_declaration_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2840 def reg_declaration_parse # puts "reg_declaration_parse" unless self.get_token(REG_REX) then return nil end sign = self.get_token(SIGNED_REX) range = self.range_parse list_of_register_variables = self.list_of_register_variables_parse self.parse_error("semicolon exptected HERE #4") unless self.get_token(SEMICOLON_REX) return reg_declaration_hook(sign,range,list_of_register_variables) end |
#register_variable_hook(name, constant_expression1, constant_expression2) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3108 def register_variable_hook(name, constant_expression1, constant_expression2) return AST[:register_variable, name, constant_expression1, constant_expression2, self.property_hook ] end |
#register_variable_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3081 def register_variable_parse parse_state = self.state name_of_memory = self.name_of_memory_parse if self.get_token(OPEN_BRA_REX) then constant_expression1 = self.constant_expression_parse self.parse_error("constant expression expected") unless constant_expression1 self.parse_error("colon expected") unless self.get_token(COLON_REX) constant_expression2 = self.constant_expression_parse self.parse_error("constant expression expected") unless constant_expression2 self.parse_error("closing bracket expected") unless self.get_token(CLOSE_BRA_REX) return register_variable_hook(name_of_memory, constant_expression1, constant_expression2) else self.state = parse_state name_of_register = self.name_of_register_parse # Handle the initialization if any. if self.get_token(EQUAL_REX) then expression = self.expression_parse self.parse_error("expression expected") unless expression else expression = nil end return register_variable_hook(name_of_register,expression,nil) end end |
#rule(name) ⇒ Object
Get a rule by +name+.
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# File 'lib/HDLRuby/verilog_parser.rb', line 1354 def rule(name) return RULES[name.to_sym] end |
#run(text: nil, filename: "", compress: false) ⇒ Object
Runs the full preprocesser and parser for text to parse +text+ and/or origin file named +filename+. If +compress+ is true the compressed version of the AST will be generated.
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# File 'lib/HDLRuby/verilog_parser.rb', line 150 def run(text: nil, filename: "", compress: false) self.setup(text: text, filename: filename, compress: compress) self.preprocess self.parse end |
#scalar_constant_hook(tok) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 5477 def scalar_constant_hook(tok) return AST[:scalar_constant, tok, self.property_hook ] end |
#scalar_constant_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 5469 def scalar_constant_parse tok = self.get_token(SCALAR_CONSTANT_REX) unless tok then return nil end return self.scalar_constant_hook(tok) end |
#scalar_event_expression_hook(scalar_event_expression) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 7304 def scalar_event_expression_hook(scalar_event_expression) return AST[:scalar_event_expression, scalar_event_expression, self.property_hook ] end |
#scalar_event_expression_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 7296 def scalar_event_expression_parse # *Auth*: we use a simple expression here. The check is left to # the AST. expression = self.expression_parse return nil unless expression return self.scalar_event_expression_hook(expression) end |
#scalar_expression_hook(expression) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 5434 def scalar_expression_hook(expression) return AST[:scalar_expression, expression, self.property_hook ] end |
#scalar_expression_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 5424 def scalar_expression_parse # *Auth*: assume to be a plain expression: actually it should be # one-bit. # This is assumed to be checked at the AST level, for example # by redefinition the hook method. expression = self.expression_parse return nil unless expression return self.scalar_expression_hook(expression) end |
#scalar_timing_check_condition_hook(scalar_expression__tok, scalar_expression, scalar_constant) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 5410 def scalar_timing_check_condition_hook(scalar_expression__tok, scalar_expression, scalar_constant) return AST[:scalar_timing_check_condition, scalar_expression__tok, scalar_expression,scalar_constant, self.property_hook ] end |
#scalar_timing_check_condition_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 5388 def scalar_timing_check_condition_parse if self.get_token(TILDE_REX) then scalar_expression = self.scalar_expression_parse self.parse_error("scalar expression expected") unless scalar_expression return self.scalar_timing_check_condition_hook(TILDE_TOK, scalar_expression, nil) end scalar_expression = self.scalar_expression_parse return nil unless scalar_expression tok = self.get_token(SCALAR_TIMING_CHECK_CONDITION_REX) if tok then scalar_constant = self.scalar_constant_parse self.parse_error("scalar constant expected") unless scalar_constant return self.scalar_timing_check_condition(tok, scalar_expression, scalar_constant) end return self.scalar_timing_check_condition_hook(scalar_expression, nil,nil) end |
#sdpd_conditional_expression_hook(unary_operator__expression, expression__binary_operator, expression) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 5812 def sdpd_conditional_expression_hook(unary_operator__expression, expression__binary_operator, expression) return AST[:sdpd_conditionla_expression, unary_operator__expression, expression__binary_operator, expression, self.property_hook ] end |
#sdpd_conditional_expression_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 5792 def sdpd_conditional_expression_parse unary_operator = self._UNARY_OPERATOR_parse if unary_operator then expression = self.expression_parse self.parse_error("expression expected") unless expression return self.sdpd_conditional_expression_hook(unary_operator, expression,nil) else expression0 = self.expression_parse return nil unless expression0 binary_operator = self._BINARY_OPERATOR_parse self.parse_error("one of [#{BINARY_OPERATOR_TOKS.join(",")}] expected") unless binary_operator expression1 = self.expression_parse self.parse_error("expression expected") unless expression1 return self.sdpd_conditional_expression_hook(expression0, binary_operator, expression1) end end |
#sdpd_hook(sdpd_conditional_expression, path_description, path_delay_value) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 5778 def sdpd_hook(sdpd_conditional_expression, path_description, path_delay_value) return AST[:sdpd, sdpd_conditional_expression,path_description, path_delay_value, self.property_hook ] end |
#sdpd_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 5755 def sdpd_parse parse_state = self.state unless self.get_token(IF_REX) then self.state = parse_state return nil end self.parse_error("opening parenthesis expected") unless self.get_token(OPEN_PAR_REX) sdpd_conditional_expression = self.sdpd_conditional_expression_parse if !sdpd_conditional_expression then self.state = parse_state return nil end self.parse_error("closing parenthesis expected") unless self.get_token(CLOSE_PAR_REX) path_description = self.path_description_parse self.parse_error("path description expected") unless path_description self.parse_error("equal expected") unless self.get_token(EQUAL_REX) path_delay_value = self.path_delay_value_parse self.parse_error("path delay value expected") unless path_delay_value self.parse_error("semicolon expected") unless self.get_token(SEMICOLON_REX) return sdpd_hook(sdpd_conditional_expression,path_description, path_delay_value) end |
#seq_block_hook(name_of_block, block_declarations, statements) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 4268 def seq_block_hook(name_of_block, block_declarations, statements) return AST[:seq_block, name_of_block, block_declarations,statements, self.property_hook ] end |
#seq_block_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 4231 def seq_block_parse unless self.get_token(BEGIN_REX) then return nil end if self.get_token(COLON_REX) then name_of_block = self.name_of_block_parse self.parse_error("block name expected") unless name_of_block block_declarations = [ ] cur_block_declaration = nil loop do cur_block_declaration = self.block_declaration_parse break unless cur_block_declaration block_declarations << cur_block_declaration end statements = [] cur_statement = nil loop do cur_statement = self.statement_parse break unless cur_statement statements << cur_statement end self.parse_error("'end' expected") unless self.get_token(END_REX) return self.seq_block_hook(name_of_block,block_declarations, statements) else statements = [] cur_statement = nil loop do cur_statement = self.statement_parse break unless cur_statement statements << cur_statement end self.parse_error("'end' expected") unless self.get_token(END_REX) return self.seq_block_hook(nil,nil,statements) end end |
#sequential_entry_hook(input_list, _state, next_state) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2166 def sequential_entry_hook(input_list, _state, next_state) return AST[:sequential_entry, input_list,_state,next_state, self.property_hook ] end |
#sequential_entry_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2145 def sequential_entry_parse parse_state = self.state input_list = self.input_list_parse if !input_list or !self.get_token(COLON_REX) then self.state = parse_state return nil end parse_state = self.state _state = self.state_parse if !_state or !self.get_token(COLON_REX) then self.state = parse_state return nil end next_state = self.next_state_parse if !next_state or !self.get_token(SEMICOLON_REX) then self.state = parse_state return nil end return self.sequential_entry_hook(input_list,_state,next_state) end |
#setup(text: nil, filename: "", compress: false) ⇒ Object
Set up the parser with text to parse +text+ and/or origin file named +filename+
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# File 'lib/HDLRuby/verilog_parser.rb', line 159 def setup(text: nil, filename: "", compress: false) # Shall we load the file? if text then # The text is provided, so do not load it. @state.text = text.to_s @state.filename = filename.to_s else # Yes, load from filename. @state.filename = filename.to_s @state.text = File.read(@state.filename) end # Set the path the the files. @state.path = File.dirname(@state.filename) + "/" # Set the compress mode. @state.compress = compress ? true : false end |
#shift_term_hook(add_terms) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6335 def shift_term_hook(add_terms) if self.state.compress and add_terms.size == 1 then return add_terms[0] else return AST[:shift_term, add_terms, self.property_hook ] end end |
#shift_term_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6318 def shift_term_parse # puts "shift_term_parse" cur_add_term = self.add_term_parse return nil unless cur_add_term add_terms = [ cur_add_term ] tok = nil loop do tok = self.get_token(ADD_OPERATOR_REX) break unless tok add_terms << tok cur_add_term = self.add_term_parse self.parse_error("expression expected") unless cur_add_term add_terms << cur_add_term end return shift_term_hook(add_terms) end |
#short_comment_hook(comment_text) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6945 def short_comment_hook(comment_text) return AST[:short_comment, comment_text, self.property_hook ] end |
#short_comment_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6933 def short_comment_parse unless self.get_token(SLASH_SLASH_REX) then return nil end # *Auth*: long and short comment are separated while in the # BNF the are the same rule. comment_text = self.short_comment_text_parse self.parse_error("comment text expected") unless comment_text self.parse_error("end of line expected") unless self.get_token(EOL_REX) return self.short_comment_hook(comment_text) end |
#short_comment_text_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 6993 def short_comment_text_parse # *Auth*: long and short comment are separated while in the # BNF the are the same rule. return comment_text_hook(self.get_token(SHORT_COMMENT_TEXT_REX)) end |
#source_text_hook(elems) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 1411 def source_text_hook(elems) return AST[:source_text, elems, self.property_hook ] end |
#source_text_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 1400 def source_text_parse elems = [] cur_elem = nil loop do cur_elem = self.description_parse break unless cur_elem elems << cur_elem end return self.source_text_hook(elems) end |
#specify_block_hook(specify_items) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 4544 def specify_block_hook(specify_items) return AST[:specify_block, specify_items, self.property_hook ] end |
#specify_block_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 4529 def specify_block_parse unless self.get_token(SPECIFY_REX) then return nil end specify_items = [] cur_specify_item = nil loop do cur_specify_item = self.specify_item_parse break unless cur_specify_item specify_items << cur_specify_item end self.parse_error("'endspecify expected'") unless self.get_token(ENDSPECIFY_REX) return self.specify_block_hook(specify_items) end |
#specify_input_terminal_descriptor_hook(input_identifier, constant_expression, constant_expression2) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 4814 def specify_input_terminal_descriptor_hook(input_identifier, constant_expression, constant_expression2) return AST[:specify_input_terminal_descriptor, input_identifier, constant_expression,constant_expression2, self.property_hook ] end |
#specify_input_terminal_descriptor_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 4790 def specify_input_terminal_descriptor_parse input_identifier = self.input_identifier_parse return nil unless input_identifier unless self.get_token(OPEN_BRA_REX) then return self.specify_input_terminal_descriptor_hook( input_identifier,nil,nil) end constant_expression = self.constant_expression_parse self.parse_error("constant expression expected") unless constant_expression tok = self.get_token(CLOSE_BRA_COLON_REX) if tok == CLOSE_BRA_TOK then return self.specify_input_terminal_descriptor_hook( input_identifier,constant_expression,nil) elsif tok == COLON_TOK then constant_expression2 = self.constant_expression_parse self.parse_error("constant expression expected") unless constant_expression self.parse_error("closing bracket expected") unless self.get_token(CLOSE_BRA_REX) return self.specify_input_terminal_descriptor_hook( input_identifier,constant_expression,constant_expression2) else self.parse_error("invalid input terminal descriptor") end end |
#specify_item_hook(declaration) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 4589 def specify_item_hook(declaration) if self.state.compress then return declaration else return AST[:specify_item, declaration, self.property_hook ] end end |
#specify_item_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 4559 def specify_item_parse specparam_declaration = self.specparam_declaration_parse if specparam_declaration then return self.specify_item_hook(specparam_declaration) end path_declaration = self.path_declaration_parse if path_declaration then return self.specify_item_hook(path_declaration) end level_sensitive_path_declaration = self.level_sensitive_path_declaration_parse if level_sensitive_path_declaration then return self.specify_item_hook(level_sensitive_path_declaration) end edge_sensitive_path_declaration = self.edge_sensitive_path_declaration_parse if edge_sensitive_path_declaration then return self.specify_item_hook(edge_sensitive_path_declaration) end system_timing_check = self.system_timing_check_parse if system_timing_check then return self.specify_item_hook(system_timing_check) end sdpd = self.sdpd_parse if sdpd then return self.specify_item_hook(sdpd) end return nil end |
#specify_output_terminal_descriptor_hook(output_identifier, constant_expression, constant_expression2) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 4854 def specify_output_terminal_descriptor_hook(output_identifier, constant_expression, constant_expression2) return AST[:specify_output_terminal_descriptor, output_identifier, constant_expression,constant_expression2, self.property_hook ] end |
#specify_output_terminal_descriptor_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 4830 def specify_output_terminal_descriptor_parse output_identifier = self.output_identifier_parse return nil unless output_identifier unless self.get_token(OPEN_BRA_REX) then return self.specify_output_terminal_descriptor_hook( output_identifier,nil,nil) end constant_expression = self.constant_expression_parse self.parse_error("constant expression expected") unless constant_expression tok = self.get_token(CLOSE_BRA_COLON_REX) if tok == CLOSE_BRA_TOK then return self.specify_output_terminal_descriptor_hook( output_identifier,constant_expression,nil) elsif tok == COLON_TOK then constant_expression2 = self.constant_expression_parse self.parse_error("constant expression expected") unless constant_expression self.parse_error("closing bracket expected") unless self.get_token(CLOSE_BRA_REX) return self.specify_output_terminal_descriptor_hook( output_identifier,constant_expression,constant_expression2) else self.parse_error("invalid output terminal descriptor") end end |
#specify_terminal_descriptor_hook(specify_terminal_descriptor) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 5221 def specify_terminal_descriptor_hook(specify_terminal_descriptor) if self.state.compress then return specify_terminal_descriptor else return AST[:specify_terminal_descriptor, specify_terminal_descriptor, self.property_hook ] end end |
#specify_terminal_descriptor_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 5205 def specify_terminal_descriptor_parse specify_input_terminal_descriptor = self.specify_input_terminal_descriptor_parse if specify_input_terminal_descriptor then return self.specify_terminal_descriptor( specify_input_terminal_descriptor) end specify_output_terminal_descriptor = self.specify_output_terminal_descriptor_parse unless specify_output_terminal_descriptor then return nil end return self.specify_terminal_descriptor_hook( specify_output_terminal_descriptor) end |
#specparam_declaration_hook(list_of_param_assignments) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 4613 def specparam_declaration_hook(list_of_param_assignments) return AST[:specparam_declaration, list_of_param_assignments, self.property_hook ] end |
#specparam_declaration_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 4603 def specparam_declaration_parse unless self.get_token(SPECPARAM_REX) then return nil end list_of_param_assignments = self.list_of_param_assignments_parse self.parse_error("list of parameter assignments expected") unless list_of_param_assignments self.parse_error("semicolon expected") unless self.get_token(SEMICOLON_REX) return self.specparam_declaration_hook(list_of_param_assignments) end |
#state ⇒ Object
Get a copy of the current state.
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# File 'lib/HDLRuby/verilog_parser.rb', line 551 def state return @state.clone end |
#state=(state) ⇒ Object
Sets the current state.
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# File 'lib/HDLRuby/verilog_parser.rb', line 556 def state=(state) # @state.index = state.index # @state.lpos = state.lpos # @state.cpos = state.cpos @state = state end |
#state_hook(level_symbol) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2284 def state_hook(level_symbol) return AST[:state, level_symbol, self.property_hook ] end |
#state_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2278 def state_parse level_symbol = self._LEVEL_SYMBOL_parse return nil unless level_symbol return self.state_hook(level_symbol) end |
#statement_hook(base, arg0, arg1, arg2, arg3) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 4052 def statement_hook(base,arg0,arg1,arg2,arg3) return AST[:statement, base,arg0,arg1,arg2,arg3, self.property_hook ] end |
#statement_or_null_hook(statement) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3886 def statement_or_null_hook(statement) return AST[:statement_or_null, statement, self.property_hook ] end |
#statement_or_null_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3877 def statement_or_null_parse if self.get_token(SEMICOLON_REX) then return statement_or_null_hook(self._NULL_hook) end statement = self.statement_parse return nil unless statement return statement_or_null_hook(statement) end |
#statement_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3919 def statement_parse tok = self.get_token(STATEMENT_REX) case(tok) when IF_TOK self.parse_error("opening parenthesis expected") unless self.get_token(OPEN_PAR_REX) expression = self.expression_parse self.parse_error("expression expected") unless expression self.parse_error("closing parenthesis expected") unless self.get_token(CLOSE_PAR_REX) statement_or_null = self.statement_or_null_parse self.parse_error("statement or nothing expected") unless statement_or_null if self.get_token(ELSE_REX) then statement_or_null2 = self.statement_or_null_parse self.parse_error("statement or nothing expected") unless statement_or_null2 return statement_hook(IF_TOK,expression,statement_or_null, statement_or_null2,nil) else return statement_hook(tok,expression,statement_or_null,nil,nil) end when CASE_TOK, CASEZ_TOK, CASEX_TOK self.parse_error("opening parenthesis expected") unless self.get_token(OPEN_PAR_REX) expression = self.expression_parse self.parse_error("expression expected") unless expression self.parse_error("closing parenthesis expected") unless self.get_token(CLOSE_PAR_REX) cur_case_item = self.case_item_parse self.parse_error("closing parenthesis expected") unless cur_case_item case_items = [ cur_case_item ] loop do cur_case_item = self.case_item_parse break unless cur_case_item case_items << cur_case_item end self.parse_error("'endcase' expected") unless self.get_token(ENDCASE_REX) return self.statement_hook(tok,expression,case_items,nil,nil) when FOREVER_TOK statement = self.statement_parse self.parse_error("statement expected") unless statement return self.statement_hook(tok,statement,nil,nil,nil) when REPEAT_TOK, WHILE_TOK self.parse_error("opening parenthesis expected") unless self.get_token(OPEN_PAR_REX) expression = self.expression_parse self.parse_error("expression expected") unless expression self.parse_error("closing parenthesis expected") unless self.get_token(CLOSE_PAR_REX) statement = self.statement_parse self.parse_error("statement expression expected") unless statement return self.statement_hook(tok,expression,statement,nil,nil) when FOR_TOK self.parse_error("opening parenthesis expected") unless self.get_token(OPEN_PAR_REX) assignment = self.assignment_parse self.parse_error("assignment expected") unless assignment self.parse_error("semicolon expected") unless self.get_token(SEMICOLON_REX) expression = self.expression_parse self.parse_error("expression expected") unless expression self.parse_error("semicolon expected") unless self.get_token(SEMICOLON_REX) assignment2 = self.assignment_parse self.parse_error("assignment expected") unless assignment2 self.parse_error("closing parenthesis expected") unless self.get_token(CLOSE_PAR_REX) statement = self.statement_parse self.parse_error("statement expected") unless statement return self.statement_hook(tok,assignment,expression,assignment2, statement) when WAIT_TOK self.parse_error("opening parenthesis expected") unless self.get_token(OPEN_PAR_REX) expression = self.expression_parse self.parse_error("expression expected") unless expression self.parse_error("closing parenthesis expected") unless self.get_token(CLOSE_PAR_REX) statement_or_null = self.statement_or_null_parse self.parse_error("statement or nothing expected") unless statement_or_null return self.statement_hook(tok,expression,statement_or_null, nil,nil) when RIGHT_ARROW_TOK name_of_event = self.parse_name_of_event self.parse_error("event name expected") unless name_of_event self.parse_error("semicolon expected") unless self.get_token(SEMICOLON_REX) return self.statement_hook(tok,name_of_event,nil,nil,nil) when DISABLE_TOK name_of_task = self.name_of_task_parse if name_of_task then self.parse_error("semicolon expected") unless self.get_token(SEMICOLON_REX) return self.statement_hook(tok,name_of_task,nil,nil,nil) end name_of_block = self.name_of_block_parse if name_of_block then self.parse_error("semicolon expected") unless self.get_token(SEMICOLON_REX) return self.statement_hook(tok,name_of_block,nil,nil,nil) end self.parse_error("invalid disable") when ASSIGN_TOK, FORCE_TOK assignment = self.assignment_parse self.parse_error("assignment expected") unless assignment self.parse_error("semicolon expected") unless self.get_token(SEMICOLON_REX) return self.statement_hook(tok,assignment,nil,nil,nil) when DEASSIGN_TOK, RELEASE_TOK lvalue = self.lvalue_parse self.parse_error("left value expected") unless lvalue self.parse_error("semicolon expected") unless self.get_token(SEMICOLON_REX) return self.statement_hook(tok,lvalue,nil,nil,nil) end delay_or_event_control = self.delay_or_event_control_parse if delay_or_event_control then statement_or_null = self.statement_or_null_parse self.parse_error("statement or nothing expected") unless statement_or_null return self.statement_hook(delay_or_event_control, statement_or_null,nil,nil,nil) end seq_block = self.seq_block_parse if seq_block then return self.statement_hook(seq_block,nil,nil,nil,nil) end par_block = self.par_block_parse if par_block then return self.statement_hook(par_block,nil,nil,nil,nil) end task_enable = self.task_enable_parse if task_enable then return self.statement_hook(task_enable,nil,nil,nil,nil) end system_task_enable = self.system_task_enable_parse if system_task_enable then return self.statement_hook(system_task_enable,nil,nil,nil,nil) end blocking_assignment = self.blocking_assignment_parse if blocking_assignment then self.parse_error("semicolon expected") unless self.get_token(SEMICOLON_REX) return self.statement_hook(blocking_assignment,nil,nil,nil,nil) end non_blocking_assignment = self.non_blocking_assignment_parse if non_blocking_assignment then self.parse_error("semicolon expected") unless self.get_token(SEMICOLON_REX) return self.statement_hook(non_blocking_assignment,nil,nil,nil,nil) end return nil end |
#system_identifier_hook(tok) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 4516 def system_identifier_hook(tok) AST[:system_identifier, tok, self.property_hook ] end |
#system_identifier_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 4507 def system_identifier_parse tok = self.get_token(SYSTEM_IDENTIFIER_REX) if tok then return self.system_identifier_hook(tok) end return nil # self.parse_error("dollar-starting identifier expected") end |
#system_task_enable_hook(name_of_system_task, expressions) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 4480 def system_task_enable_hook(name_of_system_task,expressions) return AST[:system_task_enable, name_of_system_task,expressions, self.property_hook ] end |
#system_task_enable_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 4445 def system_task_enable_parse parse_state = self.state name_of_system_task = self.name_of_system_task_parse return nil unless name_of_system_task unless self.get_token(OPEN_PAR_REX) then if self.get_token(SEMICOLON_REX) then return self.system_task_enable_hook(name_of_system_task,nil) else self.state = parse_state return nil end end cur_expression = self.expression_parse # self.parse_error("expression expected") unless cur_expression if !cur_expression then # No arguments, check for closing parenthsis and semicolon # then return. self.parse_error("closing parenthesis expected") unless self.get_token(CLOSE_PAR_REX) self.parse_error("semicolon expected") unless self.get_token(SEMICOLON_REX) return self.system_task_enable_hook(name_of_system_task,[]) end expressions = [ cur_expression ] loop do unless self.get_token(COMMA_REX) then break end cur_expression = self.expression_parse self.parse_error("expression expected") unless cur_expression expressions << cur_expression end self.parse_error("closing parenthesis expected") unless self.get_token(CLOSE_PAR_REX) self.parse_error("semicolon expected") unless self.get_token(SEMICOLON_REX) return self.system_task_enable_hook(name_of_system_task,expressions) end |
#system_timing_check_hook(tok, arg0, arg1, arg2, arg3, arg4) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 5158 def system_timing_check_hook(tok,arg0,arg1,arg2,arg3,arg4) return AST[:system_timing_check, tok,arg0,arg1,arg2,arg3,arg4, self.property_hook ] end |
#system_timing_check_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 5015 def system_timing_check_parse tok = self.get_token(SYSTEM_TIMING_REX) case(tok) when SETUP_TOK, HOLD_TOK timing_check_event0 = self.timing_check_event_parse self.parse_error("timing check event expected") unless timing_check_event0 self.parse_error("comma expected") unless self.get_token(COMMA_REX) timing_check_event1 = self.timing_check_event_parse self.parse_error("timing check event expected") unless timing_check_event1 self.parse_error("comma expected") unless self.get_token(COMMA_REX) timing_check_limit = self.timing_check_limit_parse self.parse_error("timing check limit expected") unless timing_check_limit notify_register = nil if self.get_token(COMMA_REX) then notify_register = self.notify_register_parse self.parse_error("identifier expected") unless cur_notify_register end self.parse_error("closing parenthesis expected") unless self.get_token(CLOSE_PAR_REX) self.parse_error("semicolon expected") unless self.get_token(SEMICOLON_REX) return self.system_timing_check_hook(tok, timing_check_event0, timing_check_event1, timing_check_limit, notify_register, nil) when PERIOD_TOK controlled_timing_check_event = self.controlled_timing_check_event_parse self.parse_error("controlled timing check expected") unless controlled_timing_check_event self.parse_error("comma expected") unless self.get_token(COMMA_REX) timing_check_limit = self.timing_check_limit_parse self.parse_error("timing check limit expected") unless timing_check_limit notify_register = nil if self.get_token(COMMA_REX) then notify_register = self.notify_register_parse self.parse_error("identifier expected") unless cur_notify_register end self.parse_error("closing parenthesis expected") unless self.get_token(CLOSE_PAR_REX) self.parse_error("semicolon expected") unless self.get_token(SEMICOLON_REX) return self.system_timing_check_hook(tok, controlled_timing_check_event, timing_check_limit, notify_register, nil,nil) when WIDTH_TOK controlled_timing_check_event = self.controlled_timing_check_event_parse self.parse_error("controlled timing check event expected") unless controlled_timing_check_event self.parse_error("comma expected") unless self.get_token(COMMA_REX) timing_check_limit = self.timing_check_limit_parse self.parse_error("timing check limit expected") unless timing_check_limit constant_expression = nil notify_register = nil if self.get_token(COMMA_REX) then constant_expression = self.constant_expression_parse self.parse_error("constant expression expected") unless constant_expression self.parse_error("comma expected") unless self.get_token(COMMA_REX) notify_register = self.notify_register_parse self.parse_error("identifier expected") unless notify_register end self.parse_error("closing parenthesis expected") unless self.get_token(CLOSE_PAR_REX) self.parse_error("semicolon expected") unless self.get_token(SEMICOLON_REX) return self.system_timing_check_hook(tok, controlled_timing_check_event, timing_check_limit, constant_expression, notify_register, nil) when SKEW_TOK timing_check_event0 = self.timing_check_event_parse self.parse_error("timing check event expected") unless timing_check_event0 self.parse_error("comma expected") unless self.get_token(COMMA_REX) timing_check_event1 = self.timing_check_event1 self.parse_error("timing check event expected") unless timing_check_event1 timing_check_limit = self.timing_check_limit_parse self.parse_error("timing check limit expected") unless timing_check_limit notify_register = nil if self.get_token(COMMA_REX) then notify_register = self.notify_register_parse self.parse_error("identifier expected") unless cur_notify_register end self.parse_error("closing parenthesis expected") unless self.get_token(CLOSE_PAR_REX) self.parse_error("semicolon expected") unless self.get_token(SEMICOLON_REX) return self.system_timing_check_hook(tok, timing_check_event0. timing_check_event1, timing_check_limit, notify_register, nil) when RECOVERY_TOK controlled_timing_check_event = self.controlled_timing_check_event_parse self.parse_error("controlled timing check event expected") unless controlled_timing_check_event self.parse_error("comma expected") unless self.get_token(COMMA_REX) timing_check_event = self.timing_check_event_parse self.parse_error("timing check event expected") unless timing_check_event self.parse_error("comma expected") unless self.get_token(COMMA_REX) timing_check_limit = self.timing_check_limit_parse self.parse_error("timing check event expected") unless timing_check_limit notify_register = nil if self.get_token(COMMA_REX) then notify_register = self.notify_register_parse self.parse_error("identifier expected") unless cur_notify_register end self.parse_error("closing parenthesis expected") unless self.get_token(CLOSE_PAR_REX) self.parse_error("semicolon expected") unless self.get_token(SEMICOLON_REX) return self.system_timing_check_hook(tok, controlled_timing_check_event, timing_check_event, timing_check_limit, notify_register, nil) when SETUPHOLD_TOK timing_check_event0 = self.timing_check_event_parse self.parse_error("timing check event expected") unless timing_check_event0 self.parse_error("comma expected") unless self.get_token(COMMA_REX) timing_check_event1 = self.timing_check_event_parse self.parse_error("timing check event expected") unless timing_check_event1 self.parse_error("comma expected") unless self.get_token(COMMA_REX) timing_check_limit0 = self.timing_check_limit_parse self.parse_error("timing check limit expected") unless timing_check_limit0 self.parse_error("comma expected") unless self.get_token(COMMA_REX) timing_check_limit1 = self.timing_check_limit_parse self.parse_error("timing check limit expected") unless timing_check_limit1 self.parse_error("comma expected") unless self.get_token(COMMA_REX) notify_register = nil if self.get_token(COMMA_REX) then notify_register = self.notify_register_parse self.parse_error("identifier expected") unless cur_notify_register end self.parse_error("closing parenthesis expected") unless self.get_token(CLOSE_PAR_REX) self.parse_error("semicolon expected") unless self.get_token(SEMICOLON_REX) return self.system_timing_check_hook(tok, timing_check_event0, timing_check_event1, timing_check_limit0, timing_check_limit1, notify_register) else return nil end end |
#table_definition_hook(table_entries) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2076 def table_definition_hook(table_entries) return AST[:table_definition, table_entries, self.property_hook ] end |
#table_definition_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2067 def table_definition_parse unless self.get_token(TABLE_REX) then return nil end table_entries = self.table_entries_parse self.parse_error("'endtable' expected") unless self.get_token(ENDTABLE_REX) return self.table_definition_hook(table_entries) end |
#table_entries_hook(entries) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2110 def table_entries_hook(entries) return AST[:table_entries, entries, self.property_hook ] end |
#table_entries_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2087 def table_entries_parse cur_combinational_entry = self.combinational_entry_parse if cur_combinational_entry then combinational_entries = [ cur_combinational_entry ] loop do cur_combinational_entry = self.combinational_entry_parse break unless cur_combinational_entry combinational_entries << cur_combinational_entry end return table_entries_hook(combinational_entries) else cur_sequential_entry = self.sequential_entry_parse self.parse_error("sequential entry expected") unless cur_sequential_entry sequential_entries = [ cur_sequential_entry ] loop do cur_sequential_entry = self.sequential_entry_parse break unless cur_sequential_entry sequential_entries << cur_sequential_entry end return self.table_entries_hook(sequential_entries) end end |
#task_enable_hook(name_of_task, expressions) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 4434 def task_enable_hook(name_of_task,expressions) return AST[:task_enable, name_of_task,expressions, self.property_hook ] end |
#task_enable_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 4406 def task_enable_parse parse_state = self.state name_of_task = self.name_of_task_parse return nil unless name_of_task unless self.get_token(OPEN_PAR_REX) then if self.get_token(SEMICOLON_REX) then return self.task_enable_hook(name_of_task,nil) else self.state = parse_state return nil end end cur_expression = self.expression_parse self.parse_error("expression expected") unless cur_expression expressions = [ cur_expression ] loop do unless self.get_token(COMMA_REX) then break end cur_expression = self.expression_parse self.parse_error("expression expected") unless cur_expression expressions << cur_expression end self.parse_error("closing parenthesis expected") unless self.get_token(CLOSE_PAR_REX) self.parse_error("semicolon expected") unless self.get_token(SEMICOLON_REX) return self.task_enable_hook(name_of_task,expressions) end |
#task_hook(name_of_task, tf_declaration, statement_or_null) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2385 def task_hook(name_of_task, tf_declaration, statement_or_null) return AST[:task, name_of_task,tf_declaration,statement_or_null, self.property_hook ] end |
#task_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2365 def task_parse unless self.get_token(TASK_REX) then return nil else name_of_task = self.name_of_task_parse self.parse_error("semicolon expected") unless self.get_token(SEMICOLON_REX) tf_declarations = [] cur_tf_declaration = nil loop do cur_tf_declaration = self.tf_declaration_parse break unless cur_tf_declaration tf_declarations << cur_tf_declaration end statement_or_null = self.statement_or_null_parse self.parse_error("statement or nothing expected") unless statement_or_null self.parse_error("'endtask' expected") unless self.get_token(ENDTASK_REX) return self.task_hook(name_of_task,tf_declarations,statement_or_null) end end |
#terminal_hook(terminal) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3594 def terminal_hook(terminal) return AST[:terminal, terminal, self.property_hook ] end |
#terminal_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3584 def terminal_parse expression = self.expression_parse if expression then return self.terminal_hook(expression) end identifier = self._IDENTIFIER_parse return nil unless identifier return self.terminal_hook(identifier) end |
#tf_declaration_hook(declaration) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2518 def tf_declaration_hook(declaration) if self.state.compress then return declaration else return AST[:tf_declaration, declaration, self.property_hook ] end end |
#tf_declaration_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2498 def tf_declaration_parse declaration = self.parameter_declaration_parse return self.tf_declaration_hook(declaration) if declaration declaration = self.input_declaration_parse return self.tf_declaration_hook(declaration) if declaration declaration = self.output_declaration_parse return self.tf_declaration_hook(declaration) if declaration declaration = self.inout_declaration_parse return self.tf_declaration_hook(declaration) if declaration declaration = self.reg_declaration_parse return self.tf_declaration_hook(declaration) if declaration declaration = self.time_declaration_parse return self.tf_declaration_hook(declaration) if declaration declaration = self.integer_declaration_parse return self.tf_declaration_hook(declaration) if declaration declaration = self.real_declaration_parse return self.tf_declaration_hook(declaration) if declaration return nil end |
#time_declaration_hook(list_of_register_variables) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2877 def time_declaration_hook(list_of_register_variables) return AST[:time_declaration, list_of_register_variables, self.property_hook ] end |
#time_declaration_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2862 def time_declaration_parse # puts "time_declaration_parse" parse_state = self.state unless self.get_token(TIME_REX) then return nil end list_of_register_variables = self.list_of_register_variables_parse # self.parse_error("semicolon expected") unless self.get_token(SEMICOLON_REX) unless self.get_token(SEMICOLON_REX) then self.state = parse_state return nil end return time_declaration_hook(list_of_register_variables) end |
#timing_check_condition_hook(scalar_timing_check_condition) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 5368 def timing_check_condition_hook(scalar_timing_check_condition) if self.state.compress then return scalar_timing_check_condition else return AST[:timing_check_condition, scalar_timing_check_condition, self.property_hook ] end end |
#timing_check_condition_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 5351 def timing_check_condition_parse scalar_timing_check_condition = nil if self.get_token(OPEN_PAR_REX) then scalar_timing_check_condition = self.scalar_timig_check_condition_parse unless scalar_timing_check_condition then return nil end self.parse_error("closing parenthesis expected") unless self.get_token(CLOSE_PAR_REX) else scalar_timing_check_condition = self.scalar_timig_check_condition_parse return nil unless scalar_timing_check_condition end return self.timing_check_condition_hook(scalar_timing_check_condition) end |
#timing_check_event_control_hook(tok__edge_control_specifier) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 5287 def timing_check_event_control_hook(tok__edge_control_specifier) return AST[:timing_check_event_control, tok__event_control_specifier, self.property_hook ] end |
#timing_check_event_control_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 5277 def timing_check_event_control_parse tok = self.get_token(POSEDGE_NEGEDGE_REX) if tok then return self.timing_check_event_control_hook(tok) end edge_control_specifier = self.edge_control_specifier_parse return nil unless edge_control_specifier return self.timing_check_event_control_hook(edge_control_specifier) end |
#timing_check_event_hook(timing_check_event_control, specify_terminal_descriptor, timing_check_condition) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 5190 def timing_check_event_hook(timing_check_event_control, specify_terminal_descriptor, timing_check_condition) return AST[:timing_check_event, timing_check_event_control, specify_terminal_descriptor, timing_check_condition, self.property_hook ] end |
#timing_check_event_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 5170 def timing_check_event_parse parse_state = self.state timing_check_event_control = self.timing_check_event_control_parse specify_terminal_descriptor = self.specify_terminal_descriptor_parse unless specify_terminal_descriptor then self.state = parse_state return nil end unless self.get_token(AND_AND_AND_REX) then return self.timing_check_event_hook(timing_check_event_control, specify_terminal_descriptor, nil) end timing_check_condition = self.timing_check_condition_parse self.parse_error("timing check condition expected") unless timing_check_condition return self.timing_check_event_hook(timing_check_event_control, specify_terminal_descriptor, timing_check_condition) end |
#timing_check_list_hook(expression) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 5450 def timing_check_list_hook(expression) return AST[:timing_check_list, expression, self.property_hook ] end |
#timing_check_list_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 5444 def timing_check_list_parse expression = self.expression_parse return nil unless expression return self.timing_check_list_hook(expression) end |
#udp_declaration_hook(declaration) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 1989 def udp_declaration_hook(declaration) if self.state.compress then return declaration else return AST[:UDP_declaration, declaration, self.property_hook ] end end |
#udp_declaration_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 1979 def udp_declaration_parse declaration = self.output_declaration_parse return self.udp_declaration_hook(declaration) if declaration declaration = self.reg_declaration_parse return self.udp_declaration_hook(declaration) if declaration declaration = self.input_declaration_parse return self.udp_declaration_hook(declaration) if declaration return nil end |
#udp_hook(name, name_of_variables, udp_declarations, udp_initial_statement, table_definition) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 1942 def udp_hook(name, name_of_variables, udp_declarations, udp_initial_statement, table_definition) return AST[:UDP, name,name_of_variables,udp_declarations, udp_initial_statement,table_definition, self.property_hook ] end |
#udp_initial_statement_hook(output_terminal_name, init_val) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2012 def udp_initial_statement_hook(output_terminal_name,init_val) return AST[:UDP_initial_statement, output_terminal_name,init_val, self.property_hook ] end |
#udp_initial_statement_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 2003 def udp_initial_statement_parse return nil unless self.get_token(INITIAL_REX) output_terminal_name = self.output_terminal_name_parse self.parse_error("equal expected") unless self.get_token(EQUAL_REX) init_val = self.init_val_parse self.parse_error("semicolon expected") unless self.get_token(SEMICOLON_REX) return self.udp_initial_statement_hook(output_terminal_name,init_val) end |
#udp_instance_hook(name_of_udp_instance, terminals) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3556 def udp_instance_hook(name_of_udp_instance, terminals) return AST[:UDP_instance, name_of_udp_instance,terminals, self.property_hook ] end |
#udp_instance_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3531 def udp_instance_parse parse_state = self.state name_of_udp_instance = self.name_of_udp_instance_parse unless self.get_token(OPEN_PAR_REX) then self.state = parse_state return nil end cur_terminal = self.terminal_parse unless cur_terminal then self.state = parse_state return nil end terminals = [ cur_terminal ] loop do unless self.get_token(COMMA_REX) then break end cur_terminal = self.terminal_parse self.parse_error("terminal expected") unless cur_terminal terminals << cur_terminal end self.parse_error("closing parenthesis expected") unless self.get_token(CLOSE_PAR_REX) return udp_instance_hook(name_of_udp_instance,terminals) end |
#udp_instantiation_hook(name_of_udp, drive_strength, delay, udp_instances) ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3503 def udp_instantiation_hook(name_of_udp, drive_strength, delay, udp_instances) return AST[:udp_instantiation, name_of_udp,drive_strength,delay,udp_instances, self.property_hook ] end |
#udp_instantiation_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 3479 def udp_instantiation_parse # puts "udp_instantiation_parse" parse_state = self.state name_of_udp = self.name_of_udp_parse return nil unless name_of_udp drive_strength = self.drive_strength_parse delay = self.delay_parse cur_udp_instance = self.udp_instance_parse unless cur_udp_instance then self.state = parse_state return nil end udp_instances = [ cur_udp_instance ] loop do break unless self.get_token(COMMA_REX) cur_udp_instance = self.udp_instance_parse self.parse_error("UDP instance expected") unless cur_udp_instance udp_instances << cur_udp_instance end self.parse_error("semicolon expected") unless self.get_token(SEMICOLON) return udp_instantiation_hook(name_of_udp,drive_strength,delay, udp_instances) end |
#udp_name?(name) ⇒ Boolean
Tells if a name is a known UDP name.
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# File 'lib/HDLRuby/verilog_parser.rb', line 624 def udp_name?(name) return @udp_names.include?(name) end |
#udp_parse ⇒ Object
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# File 'lib/HDLRuby/verilog_parser.rb', line 1905 def udp_parse unless self.get_token(PRIMITIVE_REX) then return nil end name = self.name_of_udp_parse self.parse_error("name of UDP expected") unless name self.parse_error("opening parenthesis expected") unless self.get_token(OPEN_PAR_REX) cur_name_of_variable = self.name_of_variable_parse self.parse_error("variable name expected") unless cur_name_of_variable name_of_variables = [ cur_name_of_variable ] loop do break unless self.get_token(COMMA_REX) cur_name_of_variable = self.name_of_variable_parse self.parse_error("identifier expected") unless cur_name_of_variable name_of_variables << cur_name_of_variable end self.parse_error("closing parenthesis expected") unless self.get_token(CLOSE_PAR_REX) self.parse_error("semicolon expected") unless self.get_token(SEMICOLON_REX) udp_declarations = [] cur_udp_declaration = nil loop do cur_udp_declaration = self.udp_declaration_parse break unless cur_udp_declaration udp_declarations << cur_udp_declaration end self.parse_error("empty UDP declaration") if udp_declarations.empty? # udp_declaration+ rule udp_initial_statement = self.udp_initial_statement_parse table_definition = self.table_definition_parse self.parse_error("'endprimitive' expected") unless self.get_token(ENDPRIMITIVE_REX) # Add a know udp name. self.add_udp_name(name) # And return the corresponding AST return self.udp_hook(name,name_of_variables,udp_declarations, udp_initial_statement, table_definition) end |