Class: HDLRuby::High::Program

Inherits:
Low::Program show all
Includes:
Hmissing
Defined in:
lib/HDLRuby/hruby_high.rb,
lib/HDLRuby/hruby_rcsim.rb

Overview

Describes a program.

Constant Summary

Constants included from Hmissing

Hmissing::High, Hmissing::NAMES

Instance Attribute Summary collapse

Attributes inherited from Low::Program

#function, #language

Attributes included from Low::Hparent

#parent

Instance Method Summary collapse

Methods included from Hmissing

#method_missing

Methods inherited from Low::Program

#add_actport, #add_arrayport, #add_code, #add_inport, #add_outport, #each_actport, #each_arrayport, #each_code, #each_inport, #each_outport

Methods included from Low::Hparent

#absolute_ref, #hierarchy, #no_parent!, #scope

Constructor Details

#initialize(lang, func, &ruby_block) ⇒ Program

Create a program in language +lang+ with start function named +func+ and built through +ruby_block+.



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# File 'lib/HDLRuby/hruby_high.rb', line 2564

def initialize(lang, func, &ruby_block)
    # Create the program.
    super(lang,func)
    # Create the namespace for the program.
    @namespace = Namespace.new(self)
    # Build the program object.
    High.space_push(@namespace)
    High.top_user.instance_eval(&ruby_block)
    High.space_pop
end

Dynamic Method Handling

This class handles dynamic methods through the method_missing method in the class HDLRuby::High::Hmissing

Instance Attribute Details

#namespace ⇒ Object (readonly)

Returns the value of attribute namespace.



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# File 'lib/HDLRuby/hruby_high.rb', line 2560

def namespace
  @namespace
end

#rccode ⇒ Object (readonly)

Extends the Program class for hybrid Ruby-C simulation. NOTE: produce a low-level Code, and not program. For now, Program is a high-level interface for software description and is not ment to be simulated as is. It may hcange in the future though.



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# File 'lib/HDLRuby/hruby_rcsim.rb', line 534

def rccode
  @rccode
end

Instance Method Details

#actport(*evs) ⇒ Object

Adds new activation ports.



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# File 'lib/HDLRuby/hruby_high.rb', line 2594

def actport(*evs)
    evs.each(&method(:add_actport))
end

#arrayport(ports = {}) ⇒ Object

Adds new array ports.



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# File 'lib/HDLRuby/hruby_high.rb', line 2614

def arrayport(ports = {})
  ports.each { |k,v| self.add_arrayport(k,v) }
end

#code(*codes) ⇒ Object

Adds new code files.



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# File 'lib/HDLRuby/hruby_high.rb', line 2599

def code(*codes)
    codes.each(&method(:add_code))
end

#inport(ports = {}) ⇒ Object

Adds new input ports.



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# File 'lib/HDLRuby/hruby_high.rb', line 2604

def inport(ports = {})
  ports.each { |k,v| self.add_inport(k,v) }
end

#outport(ports = {}) ⇒ Object

Adds new output ports.



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# File 'lib/HDLRuby/hruby_high.rb', line 2609

def outport(ports = {})
  ports.each { |k,v| self.add_outport(k,v) }
end

#to_low ⇒ Object

Converts the if to HDLRuby::Low.



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# File 'lib/HDLRuby/hruby_high.rb', line 2576

def to_low
    # Create the resulting program.
    progL = HDLRuby::Low::Program.new(self.language,self.function)
    # Add the wakening events.
    self.each_actport  { |ev| progL.add_actport(ev.to_low) }
    # Add the code files.
    self.each_code   { |ev| progL.add_code(code) }
    # Add the input signals references.
    self.each_inport  { |p| progL.add_inport(p[0],p[1].to_low) }
    # Add the output signals references.
    self.each_outport { |p| progL.add_outport(p[0],p[1].to_low) }
    # Add the array signals references.
    self.each_arrayport { |p| progL.add_arrayport(p[0],p[1].to_low) }
    # Return the resulting program.
    return progL
end

#to_rcsim(rcowner) ⇒ Object

Generate the C description of the code comming from object whose C description is +rcowner+. NOTE: also update the table of signals accessed from software code.



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# File 'lib/HDLRuby/hruby_rcsim.rb', line 540

def to_rcsim(rcowner)
    # puts "to_rcsim for program=#{self}"

    # Create the code C object.
    # puts "make code with self.class=#{self.class}"
    @rccode = RCSim.rcsim_make_code(self.language.to_s, self.function.to_s)

    # Set the owner.
    RCSim.rcsim_set_owner(@rccode,rcowner)

    # Create and add the events.
    if self.each_actport.any? then
        RCSim.rcsim_add_code_events(@rccode, self.each_actport.map do|ev|
            ev.to_rcsim(@rccode)
        end)
    end

    # Create the software interface.
    if self.language == :ruby then
        # Loads the code files.
        self.each_code do |code|
          if code.is_a?(Proc)
            Object.instance_eval(&code)
          else
            Kernel.require("./"+code.to_s)
          end
        end
        # Add the input ports.
        self.each_inport do |sym, sig|
            RubyHDL.inport(sym,sig.rcsignalI)
        end
        # Add the output ports.
        self.each_outport do |sym, sig|
            RubyHDL.outport(sym,sig.rcsignalI)
        end
        # Add the array ports.
        self.each_arrayport do |sym, sig|
            RubyHDL.arrayport(sym,sig.rcsignalI)
        end
    elsif self.language == :c then
        # Loads the code file: only the last one remains.
        self.each_code do |code|
            code = code.to_s
            # Check if the file exists.
            unless File.file?(code) then
                # The code name may be not complete, 
                # try ".so", ".bundle" or ".dll" extensions.
                if File.file?(code+".so") then
                    code += ".so"
                elsif File.file?(code + ".bundle") then
                    code += ".bundle"
                elsif File.file?(code + ".dll") then
                    code += ".dll"
                else
                    # Code not found.
                    raise "C code library not found: " + code
                end
            end
            RCSim.rcsim_load_c(@rccode,code,self.function.to_s)
        end
        # Add the input ports.
        self.each_inport do |sym, sig|
            RCSim::CPorts[sym] = sig.rcsignalI
        end
        # Add the output ports.
        self.each_outport do |sym, sig|
            RCSim::CPorts[sym] = sig.rcsignalI
        end
        # Add the array ports.
        self.each_arrayport do |sym, sig|
            RCSim::CPorts[sym] = sig.rcsignalI
        end
    end


    return @rccode
end