README for bat
==============
B^2 Logic Requirements
-BAT 1.0 is designed to work only with the BLT version of B^2 Logic 3.0, available at The University of Portland.
Design Considerations
-Inputs and Outputs
*B^2 Logic's EDF netlist does not make any distinction between active low input pad and active high input pads. Thus, all input pads are assumed to be active high. It is up to the designer to include inverters in the circuit itself, or assume that the inverted external signals will be available.
*Names of Input pads, Output pads and clocks must not contain any spaces or special characters. Valid names include only standard alphanumeric characters (A..Z, a..z, 0..9).
-BUFZ Implementation Details:
*If a BUFZ is used in a circuit, only the first (top) buffer on the BUFZ instance may be used. This is consistent with BLT implementation. One external pin is consumed per BUFZ and appears as instXpin in the final ABEL code. Tristated signals within the circuit will appear as an open input when in high impedance mode. Given this situation on CMOS technology, the signal will actually float to low rather than remain high impedance, as is typical of of any inputs that are left unconnected. TTL technology will float high in the same situation. Because of this, the designer must take care to ensure that the circuit is not designed expecting a true high impedance signal internal to the circuit (this is only achieved when the output is taken directly from the output pin consumed by the buffer).
-MUX2 Implementation Details:
*If a MUX2 is used in a circuit, only the first (top) MUX on the MUX2 package may be used. This is consistent with BLT implementation.
==============
B^2 Logic Requirements
-BAT 1.0 is designed to work only with the BLT version of B^2 Logic 3.0, available at The University of Portland.
Design Considerations
-Inputs and Outputs
*B^2 Logic's EDF netlist does not make any distinction between active low input pad and active high input pads. Thus, all input pads are assumed to be active high. It is up to the designer to include inverters in the circuit itself, or assume that the inverted external signals will be available.
*Names of Input pads, Output pads and clocks must not contain any spaces or special characters. Valid names include only standard alphanumeric characters (A..Z, a..z, 0..9).
-BUFZ Implementation Details:
*If a BUFZ is used in a circuit, only the first (top) buffer on the BUFZ instance may be used. This is consistent with BLT implementation. One external pin is consumed per BUFZ and appears as instXpin in the final ABEL code. Tristated signals within the circuit will appear as an open input when in high impedance mode. Given this situation on CMOS technology, the signal will actually float to low rather than remain high impedance, as is typical of of any inputs that are left unconnected. TTL technology will float high in the same situation. Because of this, the designer must take care to ensure that the circuit is not designed expecting a true high impedance signal internal to the circuit (this is only achieved when the output is taken directly from the output pin consumed by the buffer).
-MUX2 Implementation Details:
*If a MUX2 is used in a circuit, only the first (top) MUX on the MUX2 package may be used. This is consistent with BLT implementation.